24CSM01-ESLASHP datasheet(31/63 Pages) MICROCHIP

31 / 63 page

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Preliminary

DS20006781B

-page 31

24CSM01

10.3

Write Operations in the Security

The Security register supports byte writes, page writes

and partial page writes in the upper 256 bytes of the

region. Page writes and partial page writes in the

Security register have the same page boundary

restrictions and behavior as they do in the EEPROM

region (see Section 6.2 “Page Write”).

Writing in this region requires beginning the device

address byte with ‘1011b’ (Bh), matching the hardware

client address bits (A2 and A1) to their corresponding

device address input pins, sending a “don't care” bit in

the A16 bit position and sending a logic ‘0’ to the

Read/Write Select (R/W) bit. Following the device

address byte, the word address bytes must be sent to

the device. Bits A15 and A10 must be set to logic ‘0’

and bit A11 must be set to logic ‘1’. Figure 10-2

illustrates a byte write operation in the Security register.

If an attempt is made to write to the Security register

with the WP pin held high or after the Security register

has been locked, no write cycle will occur, no data will

be written and the device will immediately accept a new

command.

FIGURE 10-2:

BYTE WRITE IN THE SECURITY REGISTER

Note:

Enhanced software write protection does

not affect write operations to the Security

MSb

123

Device Address Byte

Word Address – Byte 0

A2 A1 x

x10

ACK

from

Client

ACK

from

Client

Start by

Host

MSb

123

Word Address – Byte 1

Data Byte

A7 A6 A5 A4

D7 D6 D5 D4

A3 A2 A1

D3 D2 D1 D0 0

ACK

from

Client

ACK

from

Client

Stop by

Host

SCL

SDA

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