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24CSM01-E/P 数据表(PDF) 5 Page - Microchip Technology

部件名 24CSM01-E/P
功能描述  1-Mbit, 3.4MHz I2C Serial EEPROM with 128-Bit Serial Number and Enhanced Software Write Protection
PDF  63 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

24CSM01-E/P 数据表(HTML) 5 Page - Microchip Technology

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 2023 Microchip Technology Inc. and its subsidiaries
Preliminary
DS20006781B
-page 5
24CSM01
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = 1.7V to 5.5V
TA = -40°C to +85°C
Extended (E):
VCC = 1.7V to 5.5V
TA = -40°C to +125°C
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
1FCLK
Clock Frequency
—
1000
kHz
1.7V ≤ VCC ≤ 5.5V
—
3400
kHz
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
2THIGH
Clock High Time
400
—
ns
1.7V ≤ VCC ≤ 5.5V
60
—
ns
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
3TLOW
Clock Low Time
400
—
ns
1.7V ≤ VCC ≤ 5.5V
160
—
ns
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
4TR
SDA and SCL Rise Time
—
1000
ns
1.7V ≤ VCC ≤ 5.5V (Note 1)
5TF
SDA and SCL Fall Time
—
300
ns
1.7V ≤ VCC ≤ 5.5V (Note 1)
6THD:STA Start Condition Hold Time
250
—
ns
1.7V ≤ VCC ≤ 5.5V
160
—
ns
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
7TSU:STA Start Condition Setup Time
250
—
ns
1.7V ≤ VCC ≤ 5.5V
160
—
ns
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
8THD:DAT Data Input Hold Time
0
—
ns
Note 2
9TSU:DAT Data Input Setup Time
50
—
ns
1.7V ≤ VCC ≤ 5.5V
10
—
ns
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
10
TSU:STO Stop Condition Setup Time
250
—
ns
1.7V ≤ VCC ≤ 5.5V
160
—
ns
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
11
TSU:WP WP Setup Time
600
—
ns
12
THD:WP WP Hold Time
1300
—
ns
13
TAA
Output Valid from Clock
—
400
ns
1.7V ≤ VCC ≤ 5.5V
—70
ns
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
14
TBUF
Bus Free Time: Bus Time
must be free before a new
transmission can start
500
—
ns
1.7V ≤ VCC ≤ 5.5V
15
TSP
Input Filter Spike Suppression
(SDA and SCL pins)
—
100
ns
1.7V ≤ VCC ≤ 5.5V (Note 3)
—10
ns
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled (Note 3)
16
TWC
Write Cycle Time
(byte or page)
—5
ms
Note 1: The rise/fall times must be less than the specified maximums to achieve the maximum clock frequencies
specified for FCLK. Please refer to the I2C specification for applicable timings.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region of
the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: Not 100% tested. CB = total capacitance of one bus line in pF.



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