24CSM01-ESLASHP datasheet(10/63 Pages) MICROCHIP

10 / 63 page

24CSM01

DS20006781B

-page 10

Preliminary

 2023 Microchip Technology Inc. and its subsidiaries

3.3

Device Addressing

Communication with the 24CSM01 begins with an 8-bit

device address byte comprised of a 7-bit client address

and a Read/Write Select (R/W) bit. Since multiple client

devices can reside on the serial bus, each client device

must have its own unique address so that the host can

access each device independently.

The 7-bit client address can be constructed in two

ways. Most communications utilize a 4-bit device type

identifier, followed by a 2-bit hardware client address

and a 1-bit MSb (Most Significant bit) address bit.

Following the A2 and A1 hardware client address bits

is bit A16 (bit 1 of the device address byte), which is the

Most Significant bit of the memory array word address.

Refer to Table 6-1 to review the bit position.

Additionally, the 24CSM01 can accept a reserved 7-bit

host code, which is then followed by a device type

identifier and hardware client address. This 7-bit host

code enables access to different modes of operation

within the device.

The 24CSM01 will respond to only specific device type

identifiers, as shown in Section 3.3.1 “Valid Device

Address Byte Inputs”.

The 2-bit hardware client address is comprised of bits

A2 and A1. These bits can be used to expand the

address space by allowing up to four devices with the

same device type identifiers on the bus. These

hardware client address bits must correlate with the

logic level on the corresponding hardwired device

address input pins, A2 and A1.

The device will respond to all valid device address byte

combinations that it receives, except in cases where

the host code sequence specifically calls for no

response.

3.3.1

VALID DEVICE ADDRESS BYTE

INPUTS

The 24CSM01 will respond to two different device type

identifiers as well as two reserved host codes as shown

in Table 3-2.

TABLE 3-1:

DEVICE ADDRESS BYTE STRUCTURE

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2

A16

Bit 0

4-Bit Device Type Identifier

2-Bit Hardware

Client Address

1-Bit

Memory

Address

Read/Write

Select

7-Bit Reserved Host Code

TABLE 3-2:

TABLE OF VALID DEVICE ADDRESS BYTES

Access Region

Device Address

Byte Type

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1-Mbit EEPROM

Device Type Identifier +

Hardware Address

A16

R/W

Security Register(1)

A16

R/W

Configuration Register(1)

A16

R/W

Manufacturer Identification(2)

Reserved Host Code

111

R/W

High-Speed (HS) Mode(3)

001

Note 1: Accessing the Security or Configuration register is only possible if any sequence or command to the main

EEPROM (if one has been sent) has been properly terminated with a Stop condition. Without proper

termination of the previous sequence, all communications with the Security or Configuration registers will

not execute successfully.

2: See Section 11.0 “Manufacturer Identification Register” for details.

3: See Section 8.0 “High-Speed Mode” for details.

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