AD8155ACPZ-R7 datasheet(30/35 Pages) AD

30 / 35 page

AD8155

Data Sheet

Rev. A | Page 30 of 35

SUPPLY SEQUENCING

Ideally, all power supplies should be brought up to the appropriate

levels simultaneously (power supply requirements are set by the

supply limits in Table 1 and the absolute maximum ratings

listed in Table 3). In the event that the power supplies to the

AD8155 are brought up separately, the supply power-up sequence

is as follows: DVCC is powered first, followed by VCC, and lastly

VTTI and VTTO. The power-down sequence is reversed, with VTTI

and VTTO being powered off first.

VTTI and VTTO contain ESD protection diodes to the VCC power

domain (see Figure 38 and Figure 39). To avoid a sustained

high current condition in these devices (ISUSTAINED < 64 mA), the

VTTI and VTTO supplies should be powered on after VCC and

should be powered off before VCC.

If the system power supplies have a high impedance in the

powered off state, then supply sequencing is not required

provided the following limits are observed:



Peak current from VTTI or VTTO to VCC < 200 mA



Sustained current from VTTI or VTTO to VCC < 64 mA

SINGLE SUPPLY vs. MULTIPLE SUPPLY

OPERATION

The AD8155 supports a flexible supply voltage of 1.8 V to 3.3 V.

For some dc-coupled links, 1.2 V or ground-referenced signaling

may be desired. In these cases, the AD8155 can be run with a

split supply configuration. An example is shown in Figure 47.

VTTO

VCC

DVCC

50Ω

VTTI

CML

AD8155

VEE = –3.3V (OR –1.8V)

VOH = 0mV

VOL = –400mV

–

MCU

MCU_VDD

MCU_VSS

DVCC

TO AD8155

I2C_SCL

I2C_SDA

VEE

ADuM1250

Figure 47. Multiple Supply Operation

Table 21. Alternate Supply Configuration Examples

Signal Level

VCC, VTTI, VTTO

VEE

1.2 V CML

1.2 V

−2.1 V ≤VEE ≤ −0.6 V

GND − 400 mV diff

GND

−3.3 V ≤VEE ≤ −1.8 V

The AD8155 control signals are always referenced between

DVCC and VEE and, when using a split supply configuration,

logic level-shift circuits should be used. The evaluation board

design shows the use of the Analog Devices, Inc., ADUM1250

I2C isolator and a level shifter to level-shift the SCL and SDA

signals (for information about the evaluation board, see the

Ordering Guide).

Evaluation of DC-Coupled Links

When evaluating the AD8155 dc-coupled, note that most lab

equipment is ground referenced whereas the AD8155 high

speed I/O are connected by 50 Ω on-die termination resistors

to VTTI and VTTO. To interface the AD8155 to ground-

referenced, high speed instrumentation (for example, the 50 Ω

inputs of a high speed oscilloscope), it is necessary to level-shift the

outputs by either using a dc-blocking network or powering the

AD8155 between ground and a negative supply.

For example, to evaluate 1.8 V dc-coupled transmitter perfor-

mance with a 50 Ω ground-referenced oscilloscope, use the

following supply configuration:

VCC = VTTO = VTTI = Ground

VEE = −1.8 V

Ground < DVCC < 1.5 V

INITIALIZATION SEQUENCE FOR LOW POWER

AND LOS_INT OPERATION

The following programming sequence is required to initialize

the device in a low power mode and to enable the LOS_INT:

set the reserved bits to Logic 1 in the RX and TX control

registers by writing the value 0x0C to the 0x40, 0x48, 0x80,

0x88, 0xC0, and 0xC8 registers.

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