AD8155ACPZ-R7 datasheet(22/35 Pages) AD

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AD8155

Data Sheet

Rev. A | Page 22 of 35

Speed Select

The SEL4G pin lets the user lower the transmitter frequency of

maximum boost from 3.25 GHz to 2.0 GHz, allowing the AD8155

to offer exceptional transmit channel compensation for legacy

applications (4.5 Gbps and slower). SEL4G = 1 lowers the

frequency of maximum boost without sacrificing the amount

of boost delivered.

AD8155 POWER CONSUMPTION

There are several sections of the AD8155 that draw varying

power depending on the supply voltages, the type of I/O coupling

used, and the status of the AD8155 operation. Figure 40 shows a

block diagram of these sections. An initialization sequence is

required to enable the AD8155 in a low power mode (see the

Applications Information section).

The first section consists of the input termination resistors. The

power dissipated in the termination resistors is due to the input

differential swing and any common-mode current resulting

from dc-coupling the input.

In the next section (the receiver section), each input is powered

only when it is selected, and the disable bits are set to 0. If a

receiver is not selected, it is powered down. Thus, the total

number of active inputs affects the total power consumption.

Furthermore, the loss-of-signal detection circuits can be disabled

independent of the receiver for even greater power savings.

The core of the device performs the multiplexer and

demultiplexer switching functions. It draws a fixed quiescent

current of 2 mA whenever the AD8155 is powered from VCC

to VEE. The switch draws an additional 4 × 4.6 mA in normal

mux/demux operation and an additional 6 × 4.6 mA with all

ports in loop-back or with bicast selected. The switch core can

be disabled to save power.

An output predriver section draws a current, IPRED, that is related to

the programmed output current, ITTO. The predriver current

always flows from VCC to VEE. It is treated separately from the

output current, which flows from VTTO and may not be the

same voltage as VCC.

The final section is the outputs section. For an individual output,

the programmed output current flows through two separate

paths. One is the on-chip termination resistor, and the other is

the transmission line and the destination termination resistor.

The nominal parallel impedance of these two paths is 25 Ω. The

sum of these two currents flows through the switches and the

current source of the AD8155 output circuit and out through VEE.

The power dissipated in the transmission line and the destination

resistor is not dissipated in the AD8155 but must be supplied

from the power supply and is a factor in overall system power.

The current in the on-chip termination resistors and the output

current source dissipate power in the AD8155 itself.

Outputs

The output current is set by a combination of output level and

preemphasis settings (see Table 19). For the two logic switch

states, this current flows through an on-chip termination

resistor and a parallel path to the destination device and its

termination resistor. The power in this parallel path is not

dissipated by the AD8155. With preemphasis enabled, some

current always flows in both the P and N termination resistors.

This preemphasis current gives rise to an output common-

mode shift, which varies with ac-coupling or dc-coupling and

which is calculated for both cases in Table 19.

Perhaps the most direct method for calculating power dissipated in

the output is to calculate the power that would be dissipated if

all of ITOT were to flow on-die from VTTO to VEE and to subtract

from this the power dissipated off die in the destination device

termination resistors and the channel. For this purpose, the

destination device and channel can be modeled as 50 Ω load

resistors, RL, in parallel with the AD8155 termination resistors.

IP_xx

IN_xx

VTTI

VEE

AC-COUPLING CAPS

(OPTIONAL)

INPUT

TERMINATION

P =

(VIN_DIFF_RMS)2

100Ω

EQUALIZER

RECEIVER

SWITCH

LOSS OF

SIGNAL

50Ω

VTTO

IOUT

VTT

50Ω

OUTPUT

TERMINATIONS

P =

× 50Ω

IOUT

OPTIONAL COUPLING

CAPACITORS

P = (VOL) (IOUT)

VOL = VTTO – (IOUT × 25Ω)

VCC

DVCC

Figure 40. AD8155 Power Distribution Block Diagram

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