Data Sheet

ADIN2299

SPECIFICATIONS

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Rev. D | 7 of 21

SPI Follower Interface Timing

Table 6 and Figure 5 describe the SPI port follower timing specifications. Note that, in SPI follower mode, the SPI clock is supplied externally

(fSPICLKEXT). To calculate the timing for the external SPI clock, use the following equation:

tSPICLKEXT = 1/fSPICLKEXT

Table 6. SPI Port Follower Timing

Parameter

Description

Min

Max

Unit

fSPICLKEXT

SPI0_CLK Frequency

10

MHz

tSPICHS

SPI0_CLK High Period

0.5 × tSPICLKEXT – 1

ns

tSPICLS

SPI0_CLK Low Period

0.5 × tSPICLKEXT–1

ns

tSPICLK

SPI0_CLK Period

tSPICLKEXT–1

ns

tHDS

Last SPI0_CLK Edge to SPI0_SEL3_SS Not Asserted

5

ns

tSPITDS

Sequential Transfer Delay

tSPICLK – 1

ns

tSDSCI

SPI0_SEL3_SS Assertion to First SPI_CLK Edge

10.5

ns

tSSPID

Data Input Valid to SPI0_CLK Edge (Data Input Setup)

2

ns

tHSPID

SPI0_CLK Sampling Edge to Data Input Invalid

1.6

ns

tDSOE

SPI0_SEL3_SS Assertion to Data Out Active

0

14

ns

tDSDHI

SPI0_SEL3_SS Deassertion to Data High Impedance

0

12.5

ns

tDDSPID

SPI0_CLK Edge to Data Out Valid (Data Out Delay)

14

ns

tHDSPID

SPI0_CLK Edge to Data Out Invalid (Data Out Hold)

0

ns

Figure 5. SPI Follower Timing