Data Sheet

ADIN2299

THEORY OF OPERATION

analog.com

Rev. D | 17 of 21

Figure 14. Indirect Connection

Table 15. Ethernet Applications Interface Signals

Mnemonic

Direction

Description

ETH0_REFCLK

Input

EMAC0 Reference Clock. Externally supplied Ethernet clock.

ETH0_CRS

Input

EMAC0 Carrier Sense. Multiplexed on alternate clock cycles.

Input

CRS: asserted by the PHY when either the transmit or receive medium is not idle. Deasserted when both are idle.

Input

RXDV: asserted by the PHY when the data on RXD0 is valid.

ETH0_RXD0

Input

EMAC0 Receive Data 0. Receive data bus.

ETH0_RXD1

Input

EMAC0 Receive Data 1. Receive data bus.

ETH0_TXEN

Input and output

EMAC0 Transmit Enable. When asserted, ETH0_TXEN indicates that the data on TXD0 is valid.

ETH0_TXD0

Output

EMAC0 Transmit Data 0. Transmit data bus.

ETH0_TXD1

Output

EMAC0 Transmit Data 1. Transmit data bus.