Data Sheet

ADIN2299

THEORY OF OPERATION

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Rev. D | 14 of 21

INDUSTRIAL ETHERNET CONNECTION

The ADIN2299 application circuit shown in Figure 16 includes

magnetics and a connector with link status and activity LEDs for

each Ethernet port.

The ADIN2299 module provides two PHYs to connect to the indus-

trial Ethernet network.

See Table 10 for the ADIN2299 connections to the RJ-45 and

Ethernet connectors on the user board as also shown in Figure 16.

Table 10. ADIN2299 Connections to the RJ-45 and Ethernet Connectors

Ball No.

Mnemonic

U2

P1_RD_N

U3

P1_RD_P

U4

P1_TD_N

U5

P1_TD_P

U13

P2_RD_N

U14

P2_RD_P

U15

P2_TD_N

U16

P2_TD_P

APPLICATIONS PROCESSOR INTERFACE

The applications processor interface is selected via the LT0 to LT2

balls as shown in Table 11. Keep LT2, LT1, and LT0 at ground when

the communication interface is selected by the board configuration

file. An option is available to override the pin configuration via the

Link Configuration File. See the RPG2 Hardware Design Integration

Guide for more details on the Link Configuration File.

For the communication protocol and information regarding how to

interface the application processor to the ADSP-CM409F on the

ADIN2299, see the RPG2 Unified Interface User Guide.

Table 11. Unified Interface Link Type Selection

LT2

LT1

LT0

Unified Interface Link Type

0

0

0

Ethernet

0

0

1

Reserved

0

1

0

SPI

0

1

1

Reserved

1

0

0

UART0

1

0

1

Reserved

1

1

0

Reserved

1

1

1

Reserved

UART Applications Processor Interface

If the UART interface is selected, connect the applications process-

or interface to the ADIN2299 module as shown in Figure 8 using

the balls indicated in Table 12. The UART is configured for 115,200

bps to 1,000,000 bps with 8 data bits, no parity, one start bit, and

one stop bit.

Figure 8. UART Applications Processor Interface

Table 12. UART Applications Processor Interface Balls

Mnemonic

Direction

Description

UART0_TX

Output

UART0 transmit output

UART0_RX

Input

UART0 receive input

SPI Applications Processor Interface

If the SPI is selected, connect the applications processor interface

to the ADIN2299 module as shown in Figure 12 using the balls

indicated in Table 14. The SPI follower connection supports a

10 MHz maximum clock rate with the clock phase bit (CPHA) =

0, so that data is captured on the leading edge, and the clock

polarity bit (CPOL) = 0 with the leading clock edge rising, and this

timing is described in the SPI Follower Interface Timing section.

The Unified Interface protocol is described in the Unified Interface

Control Document User Guide.

It is critical when a user is using the SPI that the user understands

the following regarding the BUSY and RREQ signals:

►

For the BUSY signal, the following is applicable:

►

A falling edge on BUSY indicates that transaction processing

is complete, and that the SPI follower is ready for the next

transaction.

►

Figure 11 shows the multitransaction read operation sequence

in detail.

►

BUSY is only used to pace the rate at which SPI transactions

occur. BUSY is not raised or lowered for other purposes.

►

BUSY always goes inactive after a SPI transaction, and there

are no cases in which BUSY goes high and stays high.

►

If a SPI transaction initiates while BUSY is high, undefined

behavior may result.

►

Due to underlying hardware and software constraints and

considerations, some jitter on BUSY is expected.

►

BUSY becomes active (high) no sooner than 1.14 μs after

SPI0_SEL3_SS goes inactive (high). BUSY stays active (high)

for at least

3.3 µs.

►

For the RREQ signal, the following is applicable:

►

A rising edge of this signal requires the SPI leader to acknowl-

edge the read request with a short SPI transaction before the

data can be read. After the read request is acknowledged, the

SPI follower drops RREQ to indicate that the data is ready to

be read.