Data Sheet

ADIN2299

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

analog.com

Rev. D | 10 of 21

Table 9. Ball Function Descriptions (Continued)

Ball No.

Mnemonic

Direction

Description

M15, N15, N16, N17, P1, P2,

P3, P4, P14, R4, R7, R8, R10,

R11, R14, T2, T3, T4, T5, T9,

T13, T14, T15, T16

A4

ETH0_RXD0

Input

Ethernet MAC 0 (EMAC0) Receive Data 0. Receive data bus.

A5

ETH0_REFCLK

Input

EMAC0 Reference Clock. Externally supplied Ethernet clock.

A6

ETH0_TXD0

Output

EMAC0 Transmit Data 0. Transmit data bus.

A7

UART0_TX/BUSY

Output

UART0 Transmit Output When UART Selected as the Applications Processor Interface

(UART0_TX).

Busy Signal When SPI Selected (BUSY). This signal indicates to the application side that the

communication side is busy. Connect a 3 kΩ pull-down resistor to the BUSY pin.

A8

CAN1_TX

Output

This ball can be left floating. It is reserved for the following future option: CAN Applications

Processor Interface Transmit (CAN1_TX).

A9

SPI0_CLK

Input

SPI0 Clock Input.

A10

DNC

Not applicable

Do Not Connect. The DNC pin is internally connected and must remain floating.

A11

JTG_TMS

Input

JTAG Mode Select. JTAG test access port mode select.

A12

JTG_TRST

Input

JTAG Reset. JTAG test access port reset.

B4

ETH0_RXD1

Input

EMAC0 Receive Data 1. Receive data bus.

B5

ETH0_TXEN

Output

EMAC0 Transmit Enable. When asserted, this ball indicates that the transmit data is valid.

B6

ETH0_TXD1

Output

EMAC0 Transmit Data 1. Transmit data bus.

B7

UART0_RX

Input

UART0 Receive. Receive input.

B8

CAN1_RX

Input

This ball can be left floating. It is reserved for the following future option: CAN Applications

Processor Interface Receive (CAN1_RX).

B9

SPI0_MISO/SPI_D0

Input and

output

SPI0 Leader In, Follower Out (SPI0_MISO). When QSPI

™ is selected, this ball has the

SPI0_D0 function, which is the Data 0 line for the QSPI.

B10

SPI0_SEL3_SS

Input

SPI0 Follower Select Input.

B11

JTG_TDO

Output

JTAG Serial Data Out. JTAG test access port data output.

B12

JTG_TDI

Input

JTAG Serial Data In. JTAG test access port data input.

B15

WP

Input

Write Protect SPI Flash. The WP ball is pulled high internally to the module, and it is

recommended to leave this pin floating.

B17

GPIO_8

Output

General-Purpose Input and Output 8. Connect a 10 kΩ pull-up resistor to the GPIO_8 ball.

C4

ETH0_CRS

Input

EMAC0 Carrier Sense. Multiplexed on alternate clock cycles.

Carrier Sense (CRS): Asserted by the PHY when either the transmit or receive medium is not

idle. Deasserted when both are idle.

Receive Divider (RXDV): Asserted by the PHY when the data on Receive Data Line 1 (RXD0)

is valid.

C5

ETH0_MDIO

Input and

output

EMAC0 Management Channel Serial Data. Bidirectional data bus for PHY control.

C6

ETH0_MDC

Output

EMAC0 Management Channel Clock. Clocks the MDC input of the PHY.

C9

SPI0_MOSI/SPI0_D1

Input and

output

SPI0 Leader Out, Follower In (SPI0_MOSI). When QSPI is selected, this ball has the SPI0_D1

function, which is the Data 1 line for the QSPI.

C11

JTG_TCK

Input

JTAG Clock. JTAG test access port clock.

C12

INT_IN

Input

Interrupt Input to Applications Processor. Connect a 4.7 kΩ pull-up resistor to the INT_IN ball.

C13

RREQ

Output

Interrupt Output to Applications Processor. Signal goes high to notify the application side that a

message is ready to be read. Connect a 3 kΩ pull-down resistor to the RREQ ball.

C16

GPIO_7

Output

General-Purpose Input and Output 7.

C17

GPIO_6

Input and

output

General-Purpose Input and Output 6.

D16

STATUS_LED2

Input and

output

The STATUS_LED2 ball goes low to activate the red LED of the optional dual-color STATUS

signal LED.