DSPIC33FJ12MC02ESS datasheet(154/284 Pages) MICROCHIP

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dsPIC33FJ12MC201/202

DS70265B-page 152

Preliminary

14.14.1

FAULT PIN ENABLE BITS

The PxFLTACON SFR have four control bits that deter-

mine whether a particular pair of PWM I/O pins is to be

controlled by the Fault input pin. To enable a specific

PWM I/O pin pair for Fault overrides, the corresponding

bit should be set in the PxFLTACON register.

If all enable bits are cleared in the PxFLTACON regis-

ter, the corresponding Fault input pin has no effect on

the PWM module and the pin can be used as a general

purpose interrupt or I/O pin.

14.14.2

FAULT STATES

The PxFLTACON Special Function Registers have

eight bits each that determine the state of each PWM

I/O pin when it is overridden by a Fault input. When

these bits are cleared, the PWM I/O pin is driven to the

inactive state. If the bit is set, the PWM I/O pin is

driven to the active state. The active and inactive

states are referenced to the polarity defined for each

PWM I/O pin (HPOL and LPOL polarity control bits).

A special case exists when a PWM module I/O pair is

in the Complementary mode and both pins are

programmed to be active on a Fault condition. The

PWMxH pin always has priority in the Complementary

mode, so that both I/O pins cannot be driven active

simultaneously.

14.14.3

FAULT PIN PRIORITY

If both Fault input pins have been assigned to control a

particular PWM I/O pin, the Fault state programmed for

the Fault A input pin takes priority over the Fault B input

pin.

14.14.4

FAULT INPUT MODES

Each of the Fault input pins has two modes of

operation:

• Latched Mode: When the Fault pin is driven low,

the PWM outputs go to the states defined in the

PxFLTACON registers. The PWM outputs remain

in this state until the Fault pin is driven high and

the corresponding interrupt flag has been cleared

in software. When both of these actions have

occurred, the PWM outputs return to normal oper-

ation at the beginning of the next PWM cycle or

half-cycle boundary. If the interrupt flag is cleared

before the Fault condition ends, the PWM module

waits until the Fault pin is no longer asserted to

restore the outputs.

• Cycle-by-Cycle Mode: When the Fault input pin

is driven low, the PWM outputs remain in the

defined Fault states for as long as the Fault pin is

held low. After the Fault pin is driven high, the

PWM outputs return to normal operation at the

beginning of the following PWM cycle or

half-cycle boundary.

The operating mode for each Fault input pin is selected

using the FLTAM control bits in the PxFLTACON

Special Function Registers.

Each of the Fault pins can be controlled manually in

software.

14.15 PWM Update Lockout

For a complex PWM application, the user application

may need to write up to three Duty Cycle registers and

the PWM Time Base Period register, PxTPER, at a

given time. In some applications, it is important that all

buffer registers be written before the new duty cycle

and period values are loaded for use by the module.

The PWM update lockout feature is enabled by setting

the UDIS control bit in the PWM1CON2 SFR. The

UDIS bit affects all Duty Cycle Buffer registers and the

PWM Time Base Period register, PxTPER. No duty

cycle changes or period value changes will have effect

while UDIS = 1.

If the IUE bit is set, any change to the Duty Cycle

registers will be immediately updated regardless of the

UDIS bit state. The PWM Period register (PxTPER)

updates are not affected by the IUE control bit.

Note:

The Fault pin logic can operate indepen-

dent of the PWM logic. If all the enable bits

in the PxFLTACON registers are cleared,

then the Fault pin(s) could be used as gen-

eral purpose interrupt pin(s). Each Fault

pin has an interrupt vector, interrupt flag bit

and interrupt priority bits associated with it.

DSPIC33FJ12MC02ESS 数据表(PDF) 154 Page - Microchip Technology

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