DSPIC33FJ12MC02ESS datasheet(150/284 Pages) MICROCHIP

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dsPIC33FJ12MC201/202

DS70265B-page 148

Preliminary

FIGURE 14-3:

EDGE-ALIGNED PWM

14.6

Center-Aligned PWM

Center-aligned PWM signals are produced by the

module when the PWM time base is configured in an

Up/Down Count mode (see Figure 14-4).

The PWM compare output is driven to the active state

when the value of the Duty Cycle register matches the

value of PxTMR and the PWM time base is counting

downward (PTDIR = 1). The PWM compare output is

driven to the inactive state when the PWM time base is

counting upward (PTDIR = 0) and the value in the

PxTMR register matches the duty cycle value.

If the value in a particular Duty Cycle register is zero,

the output on the corresponding PWM pin is inactive for

the entire PWM period. In addition, the output on the

PWM pin is active for the entire PWM period if the value

in the Duty Cycle register is equal to the value held in

the PxTPER register.

FIGURE 14-4:

CENTER-ALIGNED PWM

14.7

PWM Duty Cycle Comparison

Units

Three 16-bit Special Function Registers (PxDC1,

PxDC2, PxDC3) are used to specify duty cycle values

for the PWM module.

The value in each Duty Cycle register determines the

amount of time that the PWM output is active. The Duty

Cycle registers are 16 bits wide. The Least Significant

bit (LSb) of a Duty Cycle register determines whether

the PWM edge occurs in the beginning. Thus the PWM

resolution is effectively doubled.

14.7.1

DUTY CYCLE REGISTER BUFFERS

The three PWM Duty Cycle registers are double-

buffered to allow glitchless updates of the PWM

outputs. For each duty cycle, there is a Duty Cycle

a second Duty Cycle register that holds the actual

compare value used in the present PWM period.

For edge-aligned PWM output, a new duty cycle value

will be updated whenever a match with the PxTPER

the duty cycle buffers are automatically loaded into the

Duty Cycle registers when the PWM time base is

disabled (PTEN = 0) and the UDIS bit is cleared in

PWMxCON2.

When the PWM time base is in the Up/Down Count

mode, new duty cycle values are updated when the

value of the PxTMR register is zero, and the PWM time

base begins to count upward. The contents of the duty

cycle buffers are automatically loaded into the Duty

Cycle registers when the PWM time base is disabled

(PTEN = 0).

When the PWM time base is in the Up/Down Count

mode with double updates, new duty cycle values are

updated when the value of the PxTMR register is zero,

and when the value of the PxTMR register matches the

value in the PxTPER register. The contents of the duty

cycle buffers are automatically loaded into the Duty

Cycle registers when the PWM time base is disabled

(PTEN = 0).

Period

Duty Cycle

PxTPER

PXTMR

Value

New Duty Cycle Latched

PxTPER

PTMR

Value

Period

Period/2

Duty

Cycle

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