DSPIC33FJ12MC02ESS datasheet(149/284 Pages) MICROCHIP

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Preliminary

DS70265B-page 147

dsPIC33FJ12MC201/202

14.3.4

DOUBLE UPDATE MODE

In Double Update mode (PTMOD<1:0> = 11), an inter-

rupt event is generated each time the PXTMR register

is equal to zero, as well as each time a period match

occurs. The postscaler selection bits have no effect in

this mode of the timer.

Double Update mode provides two additional functions:

• The control loop bandwidth is doubled because

the PWM duty cycles can be updated twice per

period.

• Asymmetrical center-aligned PWM waveforms can

be generated, which can be useful for minimizing

output waveform distortion in certain motor control

applications.

14.3.5

PWM TIME BASE PRESCALER

The input clock to PXTMR (FOSC/4) has prescaler

options of 1:1, 1:4, 1:16 or 1:64, selected by control bits

PTCKPS<1:0> in the PXTCON SFR. The prescaler

counter is cleared when any of the following occur:

• A write to the PXTMR register

• A write to the PXTCON register

• Any device Reset

The PXTMR register is not cleared when PXTCON is

written.

14.3.6

PWM TIME BASE POSTSCALER

The match output of PXTMR can optionally be post-

scaled through a 4-bit postscaler (which gives a 1:1 to

1:16 scaling).

The postscaler counter is cleared when any of the

following occur:

• A write to the PXTMR register

• A write to the PXTCON register

• Any device Reset

The PXTMR register is not cleared when PXTCON is

written.

14.4

PWM Period

PXTPER is a 15-bit register used to set the counting

period for the PWM time base. PXTPER is a double-

buffered register. The PXTPER buffer contents are

loaded into the PXTPER register at the following instants:

• Free-Running and Single-Shot modes: When the

PXTMR register is reset to zero after a match with

the PxTPER register.

• Up/Down Count modes: When the PxTMR

The value held in the PxTPER buffer is automatically

loaded into the PxTPER register when the PWM time

base is disabled (PTEN = 0).

The

PWM

period

can

determined

using

Equation 14-1:

EQUATION 14-1:

PWM PERIOD

If the PWM time base is configured for one of the Up/

Down Count modes, the PWM period will be twice the

value provided by Equation 14-1.

The maximum resolution (in bits) for a given device

oscillator and PWM frequency can be determined using

Equation 14-2:

EQUATION 14-2:

PWM RESOLUTION

14.5

Edge-Aligned PWM

Edge-aligned PWM signals are produced by the module

when the PWM time base is in Free-Running or Single-

Shot mode. For edge-aligned PWM outputs, the output

has a period specified by the value in PxTPER and a

duty cycle specified by the appropriate Duty Cycle reg-

ister (see Figure 14-3). The PWM output is driven active

at the beginning of the period (PxTMR = 0) and is driven

inactive when the value in the Duty Cycle register

matches PxTMR.

If the value in a particular Duty Cycle register is zero,

the output on the corresponding PWM pin is inactive

for the entire PWM period. In addition, the output on

the PWM pin is active for the entire PWM period if the

value in the Duty Cycle register is greater than the

value held in the PxTPER register.

Note:

Programming a value of 0x0001 in the

PWM Period register could generate a

continuous interrupt pulse and must be

avoided.

TPWM = TCY • (PXTPER + 1) • (PXTMR Prescale Value)

Resolution =

log (2 • TPWM/TCY)

log (2)

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