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PIC18F258-E/SP 数据表(PDF) 44 Page - Microchip Technology |
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PIC18F258-E/SP 数据表(HTML) 44 Page - Microchip Technology |
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44 / 402 page ![]() PIC18FXX8 DS41159E-page 42 © 2006 Microchip Technology Inc. EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW EXAMPLE 4-3: INSTRUCTIONS IN PROGRAM MEMORY Note: All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. TCY0TCY1TCY2TCY3TCY4TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 Instruction Opcode Memory Address — 000007h MOVLW 055h 0E55h 55h 000008h 0Eh 000009h GOTO 000006h 0EF03h, 0F000h 03h 00000Ah 0EFh 00000Bh 00h 00000Ch 0F0h 00000Dh MOVFF 123h, 456h 0C123h, 0F456h 23h 00000Eh 0C1h 00000Fh 56h 000010h 0F4h 000011h — 000012h |
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