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PIC18F258-E/SP 数据表(PDF) 92 Page - Microchip Technology |
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PIC18F258-E/SP 数据表(HTML) 92 Page - Microchip Technology |
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92 / 402 page  PIC18FXX8 DS41159E-page 90 © 2006 Microchip Technology Inc. REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP bit 7 bit 0 bit 7 IRXIP: Invalid Message Received Interrupt Priority bit 1 =High priority 0 = Low priority bit 6 WAKIP: Bus Activity Wake-up Interrupt Priority bit 1 =High priority 0 = Low priority bit 5 ERRIP: CAN bus Error Interrupt Priority bit 1 =High priority 0 = Low priority bit 4 TXB2IP: Transmit Buffer 2 Interrupt Priority bit 1 =High priority 0 = Low priority bit 3 TXB1IP: Transmit Buffer 1 Interrupt Priority bit 1 =High priority 0 = Low priority bit 2 TXB0IP: Transmit Buffer 0 Interrupt Priority bit 1 =High priority 0 = Low priority bit 1 RXB1IP: Receive Buffer 1 Interrupt Priority bit 1 =High priority 0 = Low priority bit 0 RXB0IP: Receive Buffer 0 Interrupt Priority bit 1 =High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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