PIC18F258-ESLASHSP datasheet(64/402 Pages) MICROCHIP

64 / 402 page

PIC18FXX8

DS41159E-page 62

5.5

Write Verify

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

Generally, a write failure will be a bit which was written

as a ‘1’, but reads back as a ‘0’ (due to leakage off the

cell).

5.6

Protection Against Spurious Write

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared.

Also, the Power-up Timer (72 ms duration) prevents

EEPROM write.

The write initiate sequence and the WREN bit together

reduce the probability of an accidental write during

brown-out, power glitch or software malfunction.

5.7

Operation During Code-Protect

Data EEPROM memory has its own code-protect

mechanism. External read and write operations are

disabled if either of these mechanisms are enabled.

The microcontroller itself can both read and write to the

internal data EEPROM, regardless of the state of the

code-protect configuration bit. Refer to Section 24.0

“Special

Features

the

CPU”

for

additional

information.

5.8

Using the Data EEPROM

The data EEPROM is a high-endurance, byte address-

able array that has been optimized for the storage of

frequently

changing

information

(e.g.,

program

variables or other data that are updated often).

Frequently changing values will typically be updated

more often than specification D124 or D124A. If this is

not the case, an array refresh must be performed. For

this reason, variables that change infrequently (such as

constants, IDs, calibration, etc.) should be stored in

Flash program memory. A simple data EEPROM

refresh routine is shown in Example 5-3.

EXAMPLE 5-3:

DATA EEPROM REFRESH ROUTINE

Note:

If data EEPROM is only used to store

constants and/or data that changes rarely,

an array refresh is likely not required. See

specification D124 or D124A.

CLRF

EEADR

; Start at address 0

BCF

EECON1, CFGS

; Set for memory

BCF

EECON1, EEPGD

; Set for Data EEPROM

BCF

INTCON, GIE

; Disable interrupts

BSF

EECON1, WREN

; Enable writes

Loop

; Loop to refresh array

BSF

EECON1, RD

; Read current address

MOVLW

55h

;

MOVWF

EECON2

; Write 55h

MOVLW

0AAh

;

MOVWF

EECON2

; Write AAh

BSF

EECON1, WR

; Set WR bit to begin write

BTFSC

EECON1, WR

; Wait for write to complete

BRA

$-2

INCFSZ

EEADR, F

; Increment address

BRA

Loop

; Not zero, do it again

BCF

EECON1, WREN

; Disable writes

BSF

INTCON, GIE

; Enable interrupts

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