Data Sheet

ADPA7002

APPLICATIONS INFORMATION

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Rev. A | 15 of 20

Figure 51 and Figure 52 show the two recommended typical appli-

cation circuits for the ADPA7002. Pin 3 and Pin 9 are VGG1 gate

bias control pins that are connected internally. VDD1 and VDD2, Pin

2 and Pin 10, are drain bias pins for the driver stage that are

internally connected. VDD3 and VDD4, Pin 1 and Pin 11, are drain

bias pins for the output stage that also internally connect.

The gate bias voltage can be applied to either Pin 3 or Pin 9. The

drain bias can be applied to either VDD1 and VDD3 or VDD2 and

VDD4, which results in two possible bias configuration options. With

Bias Option 1 (see Figure 51), the drain and gate voltages are

applied to Pin 9, Pin 10, and Pin 11 on the south side of the device.

With Bias Option 2 (see Figure 52), the drain and gate voltages are

applied to Pin 1, Pin 2, and Pin 3 on the north side of the device.

Capacitive bypassing is required for all pins in use.

The power supply decoupling capacitors shown in Figure 51 and

Figure 52 represent the configuration used to characterize and

qualify the device. There may be a scope to reduce the number

of capacitors, but the scope varies from system to system. It is

recommended to first remove or combine the largest capacitors that

are farthest from the device.

Figure 51. Bias Option 1

Figure 52. Bias Option 2