Data Sheet

ADPA7002

APPLICATIONS INFORMATION

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Rev. A | 17 of 20

Figure 54. Application Circuit using the HMC980LP4E to Control the Drain Current of the ADPA7002

Figure 55. Application Circuit using the HMC980LP4E to Control the Drain Current of the ADPA7002 with an External Negative Voltage Source

HMC980LP4E Bias Sequence

To prevent damage to HMC980LP4E, properly sequence the dc

supply. Adhere to the following power-up sequence steps:

1. Set the VDIG pin (Pin 9) to 3.3 V.

2. Set the S1 pin (Pin 4) to 3.3 V.

3. Set the VDD pin (Pin 1) to 5.68 V.

4. Set the VNEG pin (Pin 15) to −1.5 V. This step is not needed if

using internally generated voltage.

5. Set the EN pin (Pin 5) to 3.3 V. Transitioning from 0 V to 3.3 V

turns on the VGATE pin (Pin 16) and the VDRAIN pin (Pin 17).

Adhere to the following power-down sequence steps:

1. Set EN to 0 V. Transitioning from 3.3 V to 0 V turns off VDRAIN

and VGATE.

2. Set VNEG to 0 V. This step is not required if using internally

generated voltage.

3. Set VDD to 0 V.

4. Set S1 to 0 V.

5. Set VDIG to 0 V.

When the HMC980LP4E bias control circuit is set up, the AD-

PA7002 bias can be toggled on and off by applying the VDIG pin

voltage (3.3 V) or by applying 0 V to the EN pin. When the EN

pin is set to the VDIG voltage, the VGATE pin drops to −1.5 V,

and the VDRAIN pin is turned on at +5 V. VGATE rises in voltage

until IDRAIN equals 800 mA. The closed control loop then regulates

IDRAIN at 800 mA. When EN is set to 0 V, VGATE is automatically

set to −1.5 V and VDRAIN is set to 0 V (see Figure 56 and Figure

57).