Data Sheet

ADPA7002

APPLICATIONS INFORMATION

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Rev. A | 16 of 20

BIASING PROCEDURES

Adhere to the following bias sequence during power-up:

1. Connect GND to the RF and dc ground.

2. Set the VGG1 pin voltage to −1.5 V.

3. Set the drain bias voltage pins (VDDX) to 5 V.

4. Increase the VGG1 pin voltage to achieve IDQ = 700 mA.

5. Apply the RF signal.

Adhere to the following bias sequence during power-down:

1. Turn off the RF signal.

2. Decrease VGG1 to −1.5 V to achieve IDQ = 0 mA (approximate-

ly).

3. Decrease the drain bias voltage pins (VDDX) to 0 V.

4. Decrease the VGG1 pin voltages to 0 V.

The simplified bias pin connections to the dedicated gain stages are

shown in Figure 50.

Table 8. Power Selection Table

IDQ (mA)

Gain (dB) P1dB (dBm) OIP3 (dBm)

PDISS

(W)

VGG1 (V)1, 2

600

17.2

30.04

40.6

3

−0.73

700

17.7

30.24

38.7

3.5

−0.67

800

18.0

30.25

37.0

4

−0.62

1 Data taken at the following nominal bias conditions: VDD = 5 V, TA = 25°C.

2 Adjust VGG1 from −1.5 V to 0 V to achieve the desired drain current.

The nominal bias conditions are recommended to optimize overall

performance of the ADPA7002. Unless otherwise noted, the data

in the Typical Performance Characteristics section is taken using

the nominal bias conditions. If operating at different bias conditions,

the performance of the ADPA7002 can differ from the data in Table

1, Table 2, Table 3, and Table 4. Table 8 shows how gain, P1dB,

and OIP3 vary with the bias current at 34 GHz.

BIASING THE ADPA7002 WITH THE

HMC980LP4E

The HMC980LP4E is an active bias controller designed to meet the

bias requirement for depletion mode amplifiers like the ADPA7002.

The HMC980LP4E provides constant current biasing over temper-

ature, provides device to device variation, properly sequences

the gate and drain voltages to ensure safe operation, and offers

self protection in the event of a short circuit. The HMC980LP4E

contains an internal charge pump that generates negative voltage

needed for the ADPA7002 gate and that can be used as an external

negative voltage source.

For more information regarding the usage of HMC980LP4E, refer to

the HMC980LP4E data sheet and the AN-1363 Application Note.

Figure 53. Functional Diagram of HMC980LP4E

Application Circuit Setup

Figure 54 shows a schematic of an application circuit us-

ing the HMC980LP4E to control the drain current of the ADPA7002

biased at 800 mA. In this example, the negative gate control volt-

age is generated by HMC980LP4E. Figure 55 shows an application

circuit using an external negative supply.

In the application circuit, the ADPA7002 drain voltage and drain

current are set by the following equations:

VDRAIN = VDD − (IDRAIN × 0.85 Ω)

VDRAIN = 5.68 V − (800 mA × 0.85 Ω)

VDRAIN = 5 V

and

IDRAIN = (150 Ω)/(R10)

IDRAIN = (150 Ω)/(187 Ω)

IDRAIN = 0.802 A

where:

VDRAIN is the drain voltage, or VDD.

VDD is the supply voltage to the HMC980LP4E.

IDRAIN is the output current from Pin 17 and Pin 18 on the

HMC980LP4E.

Limiting VGATE to Meet the ADPA7002 VGG1

AMR Requirement

When using the ADPA7002 with the HMC980LP4E, limit the mini-

mum voltages for VNEG and VGATE to −1.5 V to keep the voltages

within the absolute maximum ratings limit for the VGG1 pins. To limit

the minimum voltages for VNEG and VGATE, set the R15 resistor

and the R16 resistor to 732 kΩ and 632 kΩ, respectively. Refer to

the AN-1363 Application Note for more information and for the R15

and R16 calculations.