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MPX2003 数据表(PDF) 20 Page - Monolithic Power Systems

部件名 MPX2003
功能描述  Up to 140kHz All-in-One Flyback Controller with Integrated Primary Control Circuitry and Secondary Synchronous Rectification Driver
PDF  37 Pages
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制造商  MPS [Monolithic Power Systems]
网页  http://www.monolithicpower.com
标志 MPS - Monolithic Power Systems

MPX2003 数据表(HTML) 20 Page - Monolithic Power Systems

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MPX2003
– UP TO 140kHz ALL-IN-ONE FLYBACK CONTROLLER
MPX2003 Rev. 1.0
MonolithicPower.com
20
8/5/2022
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
The primary IC does not start up again until there
is a valid brown-in detection condition. Brown-in
and brownout detection are suspended when the
HV current source turns on (to avoid the effect of
the HV voltage drop). These protections can be
detected after the HV current source turns off.
Soft Start (SS)
To reduce stress on the power circuits, a soft-
start function is implemented for the primary IC.
When the primary IC enters normal start-up
mode and starts switching on its own, the
internal soft start gradually increases the current
limitation from VIPK-MIN (typically 0.1V) to VIPK-MAX
(typically 0.4V). During this time, the switching
frequency (fSW) rises from fSW-SOFT (typically
10kHz) to fSW-MAX (typically 110kHz). The soft-
start period lasts for tSOFT (typically 9.6ms).
Peak Current Control with Internal Slope
Compensation
The primary IC employs peak current mode
control with a switching on time. This on time is
controlled by comparing the voltage across the
CS
pin’s current-sense resistor with the internal
reference voltage. The reference voltage is
regulated by fSW with a maximum value of
VIPK-MAX and a minimum value of VIPK-MIN.
The reference voltage is clamped at VIPK-MAX
when fSW exceeds fSW-H (typically 60kHz); the
reference voltage is clamped at VIPK-MIN when fSW
is below fSW-L (typically 20kHz) (see Figure 3).
When fSW is between fSW-H and fSW-L, the
reference voltage is adjusted continuously.
fSW (Load)
fSW/IPK
fSW-L
fPFM-MAX
VIPK-MIN
VIPK-MAX
fSW-H
Figure 3: Peak Current Reference vs. Switching
Frequency
A synchronized positive slope is added to the
current-sense
signal
on
CS
to
prevent
subharmonic oscillations and guarantee stable
peak current mode control across a wide range
of input voltages.
Due to parasitic capacitance, a spike usually
occurs on the current-sense resistor after the
MOSFET turns on. To prevent the peak current
limitation
comparator
from
being
falsely
triggered by this turn-on spike, a leading edge
blanking (LEB) function is implemented on the
comparator. During the blanking time, the peak
current limitation comparator is disabled, so the
MOSFET cannot turn off. Two-level LEB is
adopted in the comparator. Normal operation
has tLEB-L (typically 400ns), while tLEB-S (typically
250ns) is the blanking time during SCP.
Line Compensation for Peak Current Control
Ideally, the primary peak current should be
exactly the same as the reference because of
peak current control operation. However, the IC
has a logic propagation delay and driver delay,
so the actual peak current always exceeds the
reference value. The difference between the
actual value and reference value varies with the
input voltage. A higher input voltage results in a
higher peak current overshoot (see Figure 4).
This leads to a significant variation in the
maximum power limitation.
Turn-Off Delay (tD)
VIN1/LM
VIN2/LM
IPK x RS Variation
tONP2
tONP1
VLIMIT
Figure 4: Peak Current Difference Caused by
Turn-Off Delay
The slope compensation voltage is proportional
to the primary MOSFET’s turn-on time, which is
determined by the load and input voltage. This
means that the slope compensation value is
lower when the input voltage is higher, even if
the load is the same.
To compensate for this variation and improve
overload protection (OLP) accuracy, an offset
proportional to the input voltage is added on the



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