MPX2003

– UP TO 140kHz ALL-IN-ONE FLYBACK CONTROLLER

MPX2003 Rev. 1.0

MonolithicPower.com

24

8/5/2022

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© 2022 MPS. All Rights Reserved.

compensation voltage is generated by the

transconductance amplifier. In this situation, the

external compensation network can be designed

by the COMP pin to adjust the regulation

performance.

Due to the error amplifier behavior, the COMP

voltage can indicate the output load condition,

such as when the COMP voltage rises as the

load increases.

The COMP voltage is sent to the pulse-

frequency modulation (PFM) block to modulate

the switching frequency (fSW). A lower COMP

voltage results in a lower fSW, and there are also

upper and lower limitations on the frequency

modulation. When the COMP voltage exceeds

VFS-MAX, fSW is clamped at the maximum

frequency (fPFM-MAX). When the COMP voltage is

below VBURST, the switching pulse stops until the

COMP voltage exceeds VBURST + VBURST-HYS.

fPFM-MIN is the minimum fSW corresponding to

VBURST. The first switching pulse is sent without

any delay once it exits burst mode. This closed-

loop regulation controls VOUT.

Cable Drop Compensation

The voltage drop on the cable is proportional to

the output current, which is reflected on the

voltage of the IS pin (see Figure 12). The

maximum CDC voltage on FB is VCDC_MAX. The

cable

drop

compensation

voltage

can

be

calculated with Equation (20) on page 29.

EA

FB

IS

K

VREF

Figure 12: Cable Drop Compensation

Quasi-Resonant (QR) Mode Switching

The secondary-side IC achieves quasi-resonant

(QR) mode by comparing the SRD voltage and

VDD when the converter runs in DCM. The

primary side switching is always on when the

primary side switch is near its minimum voltage.

This reduces power loss and minimizes EMI

noise.

The primary IC has a variable current limit when

fSW is below fSW-H, which means that switching is

irregular when the IC operates in QR mode. To

prevent the IC from entering this mode, the QR

is disabled when fSW is below fSW-H. At this point,

the primary side’s on signal does not wait for the

QR detection period.

The IC can immediately exit QR mode when

certain operations are detected. For example, it

exits QR mode under the following conditions:

• If CCM is required (the load becomes heavy)

• More than 6 oscillation valleys are detected

• The oscillation period during DCM lasts

longer than 20μs

• SRD has not reached VDD within 2.5μs after

the SR gate turns off

Secondary-Side Protections

Secondary Under-Voltage Lockout (SUVLO)

The secondary IC does not begin operating until

VDD rises above VDD-ON (typically 4.5V). If VDD

falls

below

VDD-OFF

(typically

4.25V),

the

secondary IC shuts down, and all internal signals

are reset. To avoid voltage spike influences

(mainly caused by the capacitor’s ESR), any

valid UVLO detection typically requires a 10μs

delay time.

Secondary Overload Protection (SOLP)

The IS pin senses the output current with

external sensing resistors. When the IS voltage

(VIS) exceeds the overload protection threshold

(VIS-OLP) and lasts longer than the overload

protection delay time (tOLP), the secondary

overload protection (SOLP) flag is set to high

and switching stops. The SOLP flag is reset

when the secondary IC or primary IC trigger

UVLO.

If the IS pin is shorted to SGND, the SOLP

function is still available, though the COMP

signal is less accurate. SOLP is implemented

based on the COMP signal. If the COMP voltage

exceeds VFS-MAX (higher than the threshold

where the switching frequency is set at the

maximum limit), the OLP timer begins counting.

SOLP is triggered after the timer runs out.

Once SOLP is triggered, COMP is internally

shorted to SGND, and it is not released until

SOLP is cleared.