MPX2003

– UP TO 140kHz ALL-IN-ONE FLYBACK CONTROLLER

MPX2003 Rev. 1.0

MonolithicPower.com

21

8/5/2022

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© 2022 MPS. All Rights Reserved.

CS signal. The offset is created by an internal

sourcing current on CS that flows across an

external resistor (RHVCS). The current source is

proportional to the HV voltage (see Figure 5).

The compensation level can be externally

adjusted by RHVCS.

CS

LEB

Ref

HV

RHVCS

IHVCS

Figure 5: Implementation of the Line

Compensation Function

The compensation current is at its maximum

value (corresponding to the HV voltage) only

when the peak current reference is at its

maximum limit. The compensation current is

removed gradually when fSW drops below fSW-H.

Compensation is removed once the peak current

reference drops below VLC-END. (see Figure 6).

fSW

IHVCS

HV

fSW-H

Figure 6: Current on the CS Pin for Line

Compensation

Driver

The driver capability is specified in the PDRV

section of the Electrical Characteristics section

on page 6. The voltage is clamped internally at

VCLAMP (typically 14.5V) to guarantee that the

external MOSFET operates safely.

Under-Voltage Lockout (UVLO)

If VCC drops below VCC-MIN (typically 8.3V), under-

voltage lockout (UVLO) stops primary switching

immediately. VCC is recharged by the current

source from HV.

Primary-Side Protections

The primary IC provides full protection features

and responds to faults on the secondary side.

If

a

protection

is

triggered,

switching

is

terminated immediately, and VCC drops. If VCC

drops to VCC-AUT, the related protection flag is

reset, and the HV current source is enabled to

charge the VCC capacitor. Then the primary IC

initiates normal start-up logic and operation.

Short-Circuit Protection (SCP)

If the CS voltage exceeds VSCP, the IC triggers

short-circuit protection (SCP), which means that

the peak current is not effectively regulated by its

limit due to a fault condition, such as winding

short circuit or output short circuit. During SCP,

auto-restart protection mode is triggered. A

reduced LEB time (tLEB-S, typically 250ns) is also

adopted by the SCP comparator to prevent a

false trigger by the turn-on spike.

For the MPX2003, the behavior during SCP is

designed as a surge-proof approach. If SCP is

triggered for the first time, the IC does not shut

down completely. Instead, primary switching is

blanked for tSCP2, during which the primary IC

does not respond to the secondary IC unless

there is a protection signal.

After the blanking time passes, the primary IC

resumes switching. If SCP is triggered for a

second time within 8 switching cycles, the

primary IC stops switching and initiates auto-

restart recovery. If the short-circuit condition is

removed after the first SCP event, the primary IC

resets the SCP counter and resumes normal

operation.

CS Short Protection (SSP)

If the CS voltage does not exceed VCSS (typically

50mV) within tSSP (typically 4.5µs) after the

primary MOSFET turns on, the primary IC

initiates CS short protection (SSP) to prevent the

primary current from overstress due to a CS

short.

SSP detection is only executed during the first

few switching cycles to prevent the CS pin or CS

resistor from being directly shorted to GND due

to improper soldering.