CS8420-CSR datasheet(82/94 Pages) CIRRUS

82 / 94 page

DS245F4

CS8420

15.1.1

Manually Accessing the E Buffer

The user can monitor the data being transferred by reading the E buffer, which is mapped into the register

space of the CS8420, via the control port. The user can modify the data to be transmitted by writing to the

E buffer.

The user can configure the interrupt enable register to cause interrupts to occur whenever D-to-E or E-to-

F buffer transfers occur. This allows determination of the allowable time periods to interact with the E buff-

er.

Also provided are D-to-E and E-to-F inhibit bits. The associated buffer transfer is disabled whenever the

user sets these bits. These may be used whenever “long” control port interactions are occurring. They can

also be used to align the behavior of the buffers with the selected audio data flow. For example, if the

audio data flow is serial port in to AES3 out, then it is necessary to inhibit D-to-E transfers, since these

would overwrite the desired transmit C data with invalid data.

Flowcharts for reading and writing to the E buffer are shown in Figures 39 and 40. For reading, since a D-

to-E interrupt just occurred, then there a substantial time interval until the next D-to-E transfer (approxi-

mately 192 frames worth of time). This is usually plenty of time to access the E data without having to

inhibit the next transfer. For writing, the sequence starts after a E-to-F transfer, which is based on the out-

put timebase. Since a D-to-E transfer could occur at any time (this is based on the input timebase), then

it is important to inhibit D-to-E transfers while writing to the E buffer until all writes are complete. Then wait

until the next E-to-F transfer occurs before enabling D-to-E transfers. This ensures that the data written

to the E buffer actually gets transmitted and not overwritten by a D-to-E transfer.

If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calcu-

lated by the CS8420, and does not have to be written into the last byte of the block by the host microcon-

troller.

block 1

block 2

block 3

block 4

block 5

block 1

block 2

block 3

block 4

block 5

Contents of E buffer

Updated at Fsi rate

Contents of F buffer

Updated from E

Output at Fso rate

Fso > Fsi (3/2) Causes blocks 1 and 3 to be transmitted twice

Fso < Fsi (2/3) Causes blocks 3 and 6 to not be transmitted

Contents of E buffer

Updated at Fsi rate

Contents of F buffer

Updated from E

Output at Fso rate

block 1

block 2

block 3

block 4

block 5

block 6

block 7

block 1

block 2

block 4

block 5

block 7

Figure 38. Channel Status Block Handling When Fso is Not Equal to Fsi

D to E interrupt occurs

Optionally set D to E inhibit

Read E data

If set, clear D to E inhibit

Return

Figure 39. Flowchart for Reading the E Buffer

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