CS8420-CSR datasheet(42/94 Pages) CIRRUS

42 / 94 page

DS245F4

CS8420

10.12 Interrupt 2 Register Mask (0Ch)

The bits of this register serve as a mask for the Interrupt 2 Register. If a mask bit is set to 1, the error is

considered unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask

bit is set to 0, the error is considered masked, meaning that its occurrence will not affect the INT pin or the

status register. The bit positions align with the corresponding bits in Interrupt Register 2. This register de-

faults to 00.

10.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh)

The two Interrupt mode registers form a 2-bit code for each Interrupt 2 register function. This code deter-

mines whether the INT pin is set active on the arrival of the interrupt condition, on the removal of the interrupt

condition, or on the continuing occurrence of the interrupt condition. These registers default to 00.

00 - Rising edge active

01 - Falling edge active

10 - Level active

11 - Reserved

76543210

VFIFOM

REUNLOCKM

DETUM

EFTUM

QCHM

UOVWM

76543210

VFIFO1

REUNLOCK1

DETU1

EFTU1

QCH1

UOVW1

VFIFO0

REUNLOCK0

DETU0

EFTU0

QCH0

UOVW0

CS8420-CSR 数据表(PDF) 42 Page - Cirrus Logic

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