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TNETE2101APZ 数据表(PDF) 33 Page - Texas Instruments

部件名 TNETE2101APZ
功能描述  10BASE-T/100BASE-TX/100BASE-FX LOW-POWER PHYSICAL-LAYER INTERFACE
PDF  39 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TNETE2101APZ 数据表(HTML) 33 Page - Texas Instruments

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TNETE2101
10BASE-T/100BASE-TX/100BASE-FX
LOW-POWER PHYSICAL-LAYER INTERFACE
SPWS032D – JANUARY 1997 – REVISED MARCH 1999
33
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MII transmit timing requirements (see Figure 21)
10BASE-T, 100BASE-TX, 100BASE-FX
NO.
PARAMETER
MIN
TYP
MAX
UNIT
1
tsu(MTXD3–MTXD0)
Setup time, MTXD3–MTXD0 valid to MTCLK
↑
10
ns
1
tsu(MTXEN)
Setup time, MTXEN valid to MTCLK
↑
10
ns
1
tsu(MTXER)
Setup time, MTXER valid to MTCLK
↑
10
ns
2
th(MTXD3–MTXD0)
Hold time, MTCLK
↑ to MTXD3–MTXD0 invalid
0
ns
2
th(MTXEN)
Hold time, MTCLK
↑ to MTXEN↓
0
ns
2
th(MTXER)
Hold time, MTCLK
↑ to MTXER↓
0
ns
3
tc(MTCLK)
Cycle time, 10BASE-T
400
ns
3
tc(MTCLK)
Cycle time, 100BASE-TX, 100BASE-FX
40
ns
MTCLK
(output)
MTXD3–MTXD0
MTXEN
MTXER
(inputs)
3
2
1
2 V
0.8 V
2 V
Figure 21. MII Transmit
MII receive timing requirements (see Figure 22)
10BASE-T, 100BASE-TX, 100BASE-FX
NO.
PARAMETER
MIN
TYP
MAX
UNIT
1
td(MRXD3–MRXD0) Delay time, MRXD3–MRXD0 valid to MRCLK↑
10
20
ns
1
td(MRXDV)
Delay time, MRXDV valid to MRCLK
↑
10
20
ns
1
td(MRXER)
Delay time, MRXER valid to MRCLK
↑
10
20
ns
1
td(MCOL)
Delay time, MCOL valid to MRCLK
↑
10
20
ns
2
tc(MRCLK)
Cycle time, 10BASE-T
400
ns
2
tc(MRCLK)
Cycle time, 100BASE-TX, 100BASE-FX
40
ns
MRCLK
(output)
MRXD3–MRXD0
MRXDV
MRXER
MCOL
(outputs)
2
2 V
0.8 V
2 V
1
Figure 22. MII Receive



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