TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

34

POST OFFICE BOX 655303

reset timing requirements (see Figure 23)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

1

tc(XTALI)

Cycle time, XTAL1

50

ns

2

tw(MRSTL)

Pulse duration

50

µs

3

tsu(MRSTL)

Setup time, MRST low before XTAL1

↑

10

ns

4

th(MRSTL)

Hold time, MRST low after XTAL1

↑

5

ns

5

td(XTALI)

Delay time, XTAL1 invalid to XTAL1 valid (stable)

25

ms

VDD

(input)

2

XTAL1

(input)

MRST*

(input)

5

1

3

4

Figure 23. Reset

At initial power up, the TNETE2101 performs an internal reset. No external reset circuit is required, however,

During operation, a full reset of the device can be performed by taking MRST terminal low for at least 50

µs.

Correct operation of the devices is not assured for a duration of 50 ms after MRST terminal is deasserted high.

100BASE-TX parameters

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Vout+

Vout+ level on transmit waveform (see Figure 24)

0.95

1.05

V

Vout–

Vout– level on transmit waveform (see Figure 24)

–1.05

–0.95

V

VTX(sym)

Vout+/Vout– symmetry (see Figure 24)

98

102

%

VTX(os)

Vout+/Vout– voltage overshoot (see Figure 24)

0

5

%

tr1(TX)

Rise time, t1 (0 –> Vout+ transition) (see Figure 25)

3

5

ns

tr2(TX)

Rise time, t4 (0 –> Vout– transition) (see Figure 25)

3

5

ns

tf1(TX)

Fall time, t2 (Vout+ transition –> 0) (see Figure 25)

3

5

ns

tf2(TX)

Fall time, t3 (Vout– transition –> 0) (see Figure 25)

3

5

ns

t

∆(TX)

Maximum tr1(Tx) – Minimum tr1(Tx), Maximum tr2(Tx) – Minimum tr2(Tx) (see Figure 25),

Maximum tf1(Tx) – Minimum tf1(Tx), Maximum tf2(Tx) – Minimum tf2(Tx)

0

0.5

ns

tDCD(TX)

Duty-cycle distortion (see Figure 26)

0

0.5

ns