TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

19

POST OFFICE BOX 655303

Table 6. PHY Generic Control Register Bit Functions

BIT

FUNCTION

NAME

NO.

FUNCTION

RESET

15

PHY reset. Writing a 1 to RESET causes the PHY to be reset and all registers (except GEN_ctl) to be reset to their

default values. RESET is self-clearing–it returns a value of 1 when read, until the internal reset is complete (which

takes no longer than 500 ms). Writing a 0 to RESET (default) has no effect. This operation can interrupt data

communications.

LOOPBK

14

Loopback. LOOPBK enables or disables internal loopback within the PHY device. When LOOPBK is set to 1, data

is wrapped internally within the PHY and does not appear on the network. When LOOPBK is cleared to 0 (default),

data is transmitted to and received from the network. While the PHY is in loopback, all network lines are placed in

a noncontentious state. If CLOOPBK is asserted low, loopback is enabled and this bit cannot be set to 0 but is read

as 1.

SPEED

13

Speed select. Link speed is determined by way of either autonegotiation or manual setting. There are three methods

by which the PHY speed can be determined:

– Autonegotiation enabled. Speed determined by negotiation.

– Autonegotiation disabled by CAUTONEG being low . Speed determined by CSPEED setting.

– Autonegotiation disabled by register bit AUTOENB set to a 0. Speed determined by register bit SPEED setting.

When SPEED is set to a 1 (default) the PHY speed is 100 Mbit/s and when set to a 0 the PHY speed is 10 Mbit/s.

The value read from the SPEED bit always reflects the current PHY speed, regardless of which method is used to

select the speed (as described previously).

AUTOENB

12

Autonegotiate enable. AUTOENB enables or disables the autonegotiation process if CAUTONEG is high. When

AUTOENB is 0, the link is configured by way of the DUPLEX and SPEED bits, and the PHY implements the

appropriate link-integrity test.

When AUTOENB is set to 1 (default), autonegotiation is enabled and the PHY engages in the autonegotiation

process when a LINK FAIL condition is detected or the AUTORSRT bit is set. The link must not be treated as valid

until the AUTOCMPLT bit and LINK bit are set to 1. If CAUTONEG terminal is low, autonegotiation is disabled, and

AUTOENB cannot be set to 1 but is read as 0.

PDOWN

11

Power down. When PDOWN is set to 1, the PHY is placed in a low power-consumption state. The time required for

the PHY to power up after PDOWN is cleared can vary considerably. It is good practice to set RESET after this time

to make certain that the PHY is in a valid state. If CPWRDOWN is asserted low, the PHY is powered down, and this

bit cannot be set to 0 but is read as 1.

ISOLATE

10

Isolate. The function of ISOLATE depends on whether the PHY is in repeater mode or node mode (determined by

the REPEATER bit in TXPHY_ctl). In node mode, when ISOLATE is set to 1 (default), the PHY electrically isolates

its data paths from the MII. In this state, it does not respond to MTXD0–MTXD3, MTXEN, and MTXER inputs, but

presents a high impedance on its MTCLK, MRCLK, MRXDV, MRXER, MRXD0–MRXD3, and MCOL outputs. It still

responds to management frames on MDIO and MDCLK. In repeater mode, when ISOLATE is set to 1, the PHY

presents a high impedance on its MRCLK, MRXDV, MRXER, and MRXD0–MRXD3 outputs only. If CISOLATE is

deasserted high, the ISOLATE function is disabled, and this bit cannot be set to 1 but is read as 0.

AUTORSRT

9

Restart autonegotiation. If autonegotiation has been enabled by setting AUTOENB to 1, the autonegotiation process

can be restarted by setting AUTORSRT to 1. AUTORSRT is self clearing, and the PHY returns a value of 1 in this

bit until autonegotiation fast-link pulse (FLP) data-burst transmission has been initiated. When AUTOENB is cleared

to 0, AUTORSRT is read as 0. The default value of AUTORSRT is 0.

DUPLEX

8

Duplex mode. Duplex mode is determined by way of either autonegotiation or normal setting. There are three ways

the PHY speed can be determined:

– Autonegotiation enabled. Duplex determined by negotiation.

– Autonegotiation disabled by CAUTONEG being low. Duplex determined by CDUPLEX setting.

– Autonegotiation disabled by register bit AUTOENB set to a 0. Duplex determined by register bit DUPLEX setting.

When DUPLEX is set to 1 (default), the PHY is in full duplex. When DUPLEX is set to 0, the PHY is in half duplex.

The value read from the DUPLEX bit always reflects the current PHY duplex, regardless of which is used to select

the duplex, (as described previously).

COLTEST

7

Collision test mode. When COLTEST is set to 1 and LOOPBK is set to 1, the PHY asserts the collision-detect signal

MCOL when transmit enable MTXEN is asserted. The default value of COLTEST is 0.

Reserved

6–0

Reserved. Read and write as 0.