TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

15

POST OFFICE BOX 655303

10BASE-T/100BASE-TX PHY registers

The IEEE Std 802.3 MII serial protocol allows for up to 32 different PMD devices, with up to 32 (16-bit-wide)

internal registers in each device. The 10BASE-T/100BASE-TX PHY implements 11 internal registers, three of

which are hardwired. Figure 4 shows the device register map. Most of the registers are the generic registers

mandated by the MII specification. The three registers (TXPHY_X) in Figure 4 are TI-specific registers. All other

registers are read as 0s.

GEN_ctl

GEN_sts

GEN_id_hi

GEN_id_lo

AN_adv

AN_lpa

AN_exp

AN_np

Reserved

Reserved

Reserved

TXPHY_id

TXPHY_ctl

TXPHY_sts

0x00h

0x01h

0x02h

0x03h

0x04h

0x05h

0x06h

0x07h

0x08h

REGISTER

ADDRESS

DESCRIPTION

Generic control (see Figure 7 and Table 6)

Generic status (see Figure 8 and Table 7)

Generic identifier (high) hardwired (see Figure 9)

Generic identifier (low) hardwired (see Figure 10)

Autonegotiation advertisement (see Figure 11 and Table 8)

Autonegotiation link partner ability (see Figure 12 and Table 9)

Autonegotiation expansion (see Figure 15 and Table 13)

Autonegotiation next-page transmit (see Figure 16 and Table 14)

•

•

•

Reserved by IEEE Std 802.3

0x0Fh

0x10h

0x11h

0x12h

PHY identifier†

PHY control (see Figure 17 and Table 15)

PHY status (see Figure 18 and Table 16)

† TI-specific register

Figure 4. Register Map