TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

28

POST OFFICE BOX 655303

Table 15. PHY Control Register Bit Functions (Continued)

BIT

FUNCTION

NAME

NO.

FUNCTION

MANCONF

13

Manual configuration. Writing a 1 to MANCONF enables manual configuration of the PHY polarity using the SWAPOL

bit. The default value of this bit is 0 which enables automatic detection of polarity by monitoring link pulses for inversion.

See the PLOK bit description in register 0

×12 for a detailed explanation.

SQEEN

12

Signal quality error (SQE) enable. When SQEEN is set to 1, the 10BASE-T PHY (when selected) performs the SQE

test function at the end-of-packet transmission. The default value of SQEEN is 1.

The SQE test provides an internal simulated collision to test collision-detect circuit integrity after a transmission. In

10BASE-T mode, the SQE test asserts MCOL between 600–1600 ns after the last positive edge of a frame is

transmitted, with the collision event lasting between 500–1500 ns.

MTEST

11

Manufacturing test. When MTEST is set to 1, the PHY is placed in manufacturing test mode. Manufacturing test mode

is reserved for TI manufacturing test only. The default value of MTEST is 0. Operation of the PHY and MII registers

is undefined when this bit is set.

FIBER

10

100BASE-FX mode. When FIBER is set to 1, PHY disables its cipher-stream scrambler and descrambler. The UTP

interface terminals are placed in a nonfunctional low-power state and the differential PECL fiber-interface terminals

are activated. The default value of FIBER is 0. If CFIBER is asserted low, the fiber interface is enabled and this bit

cannot be set to 0 but is read as 1.

FEFEN

9

Far-end fault indication enable. When both FEFEN and FIBER are set to 1, the PHY transmits the far-end fault

indication (FEFI) symbol stream (consisting of 84 1s and 0) when the 100BASE-FX signal detect is deasserted. Also,

at this time the FEFI bit in TXPHY_sts is set to 1. The FEFI system is specified for use in 100BASE-FX fiber applications

only. The default value of FEFEN is 0.

NOENDEC

8

No encode/decode. When NOENDEC is set to 1, the 100BASE-TX PHY bypasses its 5B4B encoder and decoder.

Instead, it takes the 5-bit code presented on MTXD0–MTXD3 and MTXER (most significant bit) as transmit data, and

presents the received 5B code groups on MRXD0–MRXD3 and MRXER (most significant bit). The default value of

NOENDEC is 0. This mode of operation is provided for applications test purposes.

If CPASS5B terminal is asserted low, the NOENDEC mode is enabled and this bit cannot be set to 0 but is read as 1.

NOALIGN

7

No symbol alignment. When NOALIGN is set to 1, the 100BASE-TX receive-symbol-alignment block is bypassed and

the 5-bit descrambled receive symbols are passed directly to the 5B4B decoder.

DUPONLY

6

Duplex LED. When DUPONLY is set to 1, the LDUPCOL LED driver indicates the duplex mode in which the PHY is

operating and does not indicate network collisions. The default value of DUPONLY is 0.

REPEATER

5

Repeater-mode enable. When REPEATER is set to 1, the PHY does not assert MCRS in response to transmit activity

in 100BASE-TX mode. Also, the ISOLATE bit in the GEN_ctl register causes only MRCLK, MRXD0–MRXD3, MRXDV,

and MRXER to resort to a high-impedance state. The default value of REPEATER is 0. If CREPEATER is asserted

low, the repeater mode is enabled and this bit cannot be set to 0 but is read as 1.

RXRESET

4

100BASE-TX receive reset. Writing a 1 to this self-clearing bit allows the 100BASE-TX receive logic (descrambler,

aligner, and 5B4B decoder) to be reset without affecting other parts of the PHY. The default value of RXRESET is 0.

NOLINKP

3

Disable link-pulse transmission. When NOLINKP is set to 1 and IGLINK is set to 1, the PHY does not transmit any

form of link pulses. In 10BASE-T applications, the link partner does not detect a good link and does not transmit any

data, unless it is not implementing the link-integrity test (for example, a PHY with IGLINK set to 1). Autonegotiation

should be disabled by clearing AUTOENB to 0 when NOLINKP is set because no autonegotiation FLPs are transmitted

to the link partner. NOLINKP has no effect on the PHY if IGLINK is cleared to 0. The default value of NOLINKP is 0.

This mode of operation is provided for application-test purposes.

NFEW

2

Not far end wrap. NFEW has meaning only when the LOOPBK bit of GEN_ctl is set to 1. Writing a 1 to NFEW causes

the PHY to wrap the MTXD input data to the MRXD output just after the MII interface. Writing a 0 to NFEW causes

the PMI to wrap the TX data to the RX just before the network transceiver interface (either 10BASE-T or 100BASE-TX).

When NFEW is set to 1, preamble is wrapped without degradation (in normal operation, the PHY may lose some

preamble bits during initial clock-recovery synchronization). The default value of NFEW is 0.

INTEN

1

Interrupt enable. Writing a 1 to INTEN allows the PHY to generate interrupts on the MII when the MINT bit is set to 1.

Writing a 0 to INTEN prevents the PHY from generating any MII interrupts. INTEN does not disable test interrupts. The

default value of INTEN is 0.

TINT

0

Test interrupt. When TINT is set to 1, the PHY generates interrupts on the MII, regardless of the value of the MINT

and INTEN bits. TINT is to be used for diagnostic test of the MII-interrupt function. The default value of TINT is 0.