TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

4

POST OFFICE BOX 655303

Terminal Functions (Continued)

configuration (continued)

TERMINAL

TYPE

I/O

DESCRIPTION

NAME

NO.

TYPE

I/O

DESCRIPTION

CPWRDOWN

32

TTL

I

Power-down enable. When CPWRDOWN is low, the PHY is placed in a low power-consumption

state. This function can be controlled by PHY register 0, bit 11, PDOWN, if CPWRDOWN is high.

CREPEATER

21

TTL

I

Repeater-mode enable. When CREPEATER is low, the repeater mode is enabled and the PHY

does not assert MCRS in response to transmit activity. This function can be controlled by PHY

register 0x11, bit 5, REPEATER, if CREPEATER is high.

CSPEED

34

TTL

I/O

Speed configuration. When CAUTONEG is low, CSPEED sets the PHY speed to either

10BASE-T (low) or 100BASE-TX (high). When CAUTONEG is high and autonegotiation is

complete, CSPEED is driven low if 10BASE-T mode was selected, or set at high-impedance state

if 100BASE-TX mode was selected. The PHY speed also can be controlled and read at PHY

register 0, bit 13, SPEED.

fiber interface

TERMINAL

TYPE†

I/O

DESCRIPTION

NAME

NO.

TYPE†

I/O

DESCRIPTION

FRCVN

FRCVP

79

80

PECL

I

100BASE-FX serial data input pair. Differential 3.3-V pseudo-emitter-coupled logic (PECL) 125-Mbit/s

receive-data input for fiber mode.

FSDN

FSDP

82

83

PECL

I

100BASE-FX serial data detect pair. Differential 3.3-V PECL 125-Mbit/s signal-detect input.

FXMTN

FXMTP

76

77

PECL

O

100BASE-FX serial data output pair. Differential 3.3-V PECL 125-Mbit/s serialized transmit-data

output for fiber mode.

† PECL = pseudo-emitter-coupled-logic

IEEE Std 1149.1 JTAG interface

TERMINAL

TYPE‡

I/O

DESCRIPTION

NAME

NO.

TYPE‡

I/O

DESCRIPTION

JTCLK

69

5-V TTL

I

Test clock. JTCLK is used to clock state information and test data into and out of the device during

operation of the test port.

JTDI

73

5-V TTL

I

Test data input. JTDI is used to serially shift test data and test instructions into the device during

operation of the test port.

JTDO

71

5-V TTL

O

Test data output. JTDO is used to serially shift test data and test instructions out of the device during

operation of the test port.

JTMS

68

5-V TTL

I

Test-mode select. JTMS is used to control the state of the test-port controller within the PHY.

JTRST

67

5-V TTL

I

TAP reset. JTRST is used to reset the TAP controller (optional).

‡ 5-V TTL terminals are 5-V tolerant if VDD5 is connected to 5 V.