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LT3074AVPBF 数据表(PDF) 37 Page - Analog Devices |
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LT3074AVPBF 数据表(HTML) 37 Page - Analog Devices |
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37 / 62 page ![]() Data Sheet LT3074 analog.com Rev 0. 37 of 62 SETCAP Pin Capacitance: Noise, PSRR, Transient Response, and Soft-Start In addition to reducing output noise, using a SETCAP pin capacitor also improves PSRR and transient performance. Note that any bypass-capacitor leakage deteriorates the DC regulation of the LT3074. Leakages on the SETCAP pin capacitor shunt current away from the 100µA precision reference current and also create an offset across the filter resistor. Capacitor leakage of even 100nA is more than 0.1% DC error. Therefore, Analog Devices recommends the use of good quality, low-leakage ceramic capacitors. Using the SETCAP pin capacitor also soft-starts the output and limits inrush current. Fast Start For ultralow noise applications that require low 1/f noise, a SETCAP pin capacitor with a very low frequency pole may be necessary. This significantly increases the start-up time in accordance with the RC time constant associated with the SETRES pin resistor, filter resistor, and SETCAP pin capacitor. The LT3074 incorporates fast start-up circuitry that sources the SETCAP pin with a typical current of 2mA during start-up to rapidly charge the filter capacitor, decreasing start-up time. The 2mA current source turns on if the SETRES to SETCAP differential is greater than approximately 25mV and remains engaged until the SETCAP pin voltage catches up to the SETRES pin voltage; at which point the current turns off. If the regulator is in current limit, thermal shutdown or BIAS UVLO is detected, and the fast start function is disabled. When fast start is enabled during start-up, if the SETCAP pin slew rate approaches the SETRES pin slew rate, the SETCAP pin voltage may catch up to the SETRES pin voltage while the SETRES pin voltage is still ramping. This shuts off the fast start circuit until the SETRES pin voltage can rise above the SETCAP pin voltage by 25mV. This is intended operation. This turn-on and turn-off cause stair stepping at the SETCAP pin voltage (and possibly in turn at the OUT voltage). Increasing the SETCAP pin capacitor smoothes the SETCAP pin start-up. Output Voltage Margining The LT3074 provides the capability to margin the output voltage in discrete steps from 1% to 30% using the PMBus. The margining is achieved by scaling the precision 100µA current reference supplied at the SETRES pin. Depending on the nominal output voltage and the amount of margining being used, the high side margin may enable the fast start functionality (if the SETRES to SETCAP voltage differential exceeds approximately 25mV); as a result, the output voltage rapidly settles to the margined value. For high-side margin, where the SETRES to SETCAP differential does not exceed the 25mV threshold and all low side margining, the output takes a RC delay (set by the SETRES pin resistor, approximately 1kΩ filter resistor from SETRES to SETCAP and the SETCAP pin capacitor) to settle to the margined value. See the OPERATION and MFR_MARGIN commands in the PMBus Command Details section for additional information on output voltage margining. BIAS/BIASAF/BIASDF Pin Requirements The BIASAF and BIASDF pins are internally tied to the BIAS pin through separate filter resistors. BIASAF supplies current to all the analog functional blocks and the BIASDF supplies current to the digital circuitry. This minimizes the high frequency, digital switching noise coupling to the high performance, low noise analog circuitry. The LT3074 requires a minimum 2.2µF bypass capacitor on the BIASAF pin and 0.47µF bypass capacitor on the BIASDF pin for stability and proper operation. No bypass capacitor is needed on the BIAS pin. To ensure proper operation, the BIAS voltage must satisfy the following conditions: 2.375V ≤ VBIAS ≤ 5.5V and VBIAS ≥ VOUT + 1.2V. Do not externally load the BIASAF and/or the BIASDF pins. |
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