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LT3074AVPBF 数据表(PDF) 40 Page - Analog Devices |
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LT3074AVPBF 数据表(HTML) 40 Page - Analog Devices |
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40 / 62 page ![]() Data Sheet LT3074 analog.com Rev 0. 40 of 62 Figure 87. Evaluation Board Layout High Efficiency Linear Regulator – Input-to-Output Voltage Control The VIOC pin controls an upstream switching converter to maintain a constant voltage across the LT3074, regardless of the LDO’s output voltage. This maximizes efficiency while maintaining PSRR performance. The VIOC pin is the output of a fast amplifier and equals (VIN − VOUT) + 800mV. As shown in Figure 88, the VIOC feature is simple to use. In the case of switching converters with feedback voltage, VFB ≥ 1V, connect the VIOC pin to the upstream switching converter’s feedback (FB) pin. This regulates the LT3074 device’s input-to-output differential to the switching converter’s feedback voltage minus 800mV. When paralleling multiple LT3074 devices, connect the VIOC pin of one of the LT3074 device to the switching converter’s FB pin and float all other VIOC pins. When LT3074 is turned off, VINLDO is clamped to a voltage set by VFBSWITCHER × (R1 + R2)/R1. Figure 88. Basic VIOC Operation While the VIOC buffer is inside the switching converter’s feedback loop, given the VIOC buffer’s high bandwidth, the switching converter’s frequency compensation need not be adjusted. Phase delay through the VIOC buffer is typically less than 2° for frequencies as high as 100kHz. Hence, within the switching converter’s bandwidth (usually much less than 100kHz), the VIOC buffer is transparent and acts like an ideal wire. CSETCAP 4.7µF COUT 10µF CIN RPG1 30kΩ RPG2 15kΩ RSETRES 5kΩ 800mV 51kΩ RASELTOP RASELBOT 0.47µF 2.2µF LSW R1 R2 LT3074 BIAS BIASDF IN OUT SENSE SETCAP IMON SDA SCL ALERT ASEL AGND EN VINLDO VOUTLDO = 0.5V IOUT(MAX) = 3A VIOC PG CLKDIS SETRES BIASAF DGND PGFB 1× + – VBIAS SW FB VIN EN/UV VIN UPSTREAM DC-DC CONVERTER VFB >= 1V VFBSWITCHER |
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