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LT3074AVPBF 数据表(PDF) 1 Page - Analog Devices

部件名 LT3074AVPBF
功能描述  5.5V, 3A Ultralow Noise, High PSRR, 45mV Dropout Linear Regulator with PMBus
PDF  62 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

LT3074AVPBF 数据表(HTML) 1 Page - Analog Devices

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Data Sheet
LT3074
5.5V, 3A Ultralow Noise, High PSRR, 45mV Dropout Linear Regulator with PMBus
Rev.0
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
One Analog Wa y, Wilmington, MA 01887 -2356, U.S.A.
Tel: 781.329.47 00
©2024 Analog Devices, Inc. Al l rights rese rve d.
FEATURES
Ultralow RMS Noise: 1.2µVRMS (10Hz to 100kHz)
Ultralow Spot Noise: 3.5nV/√Hz at 10kHz
Ultralow 1/f Noise: 7µVP-P (0.1Hz to 10Hz)
High PSRR at High Frequency: 52dB at 1MHz
Ultrafast Transient Response
Dropout Voltage: 45mV Typical
100µA Reference Current: ±0.5% Initial Accuracy
Precision Current Monitor: ±3% Accuracy at 3A
PMBus Capability Includes:
VOUT, IOUT, VIN, VBIAS, and Temperature Reporting
VOUT Margining
IOUT Overcurrent and Undercurrent Warn Limits
VOUT, VIN, and VBIAS Undervoltage and Overvoltage
Warn Limits
Overtemperature Warn Limit
Stable with Ceramic Output Capacitors (10μF
Minimum)
Parallel Multiple Devices for Higher Current
VIOC Pin to Control Upstream Switching Converter
22-Lead (3mm × 4mm) LQFN Package
APPLICATIONS
RF Power Supplies: PLLs, VCOs, Mixers, LNAs, PAs
High Speed/High Precision Data Converters
Low Noise Instrumentation
Post-Regulator for Switching Supplies
FPGA and DSP Power Supplies
Medical Applications
GENERAL DESCRIPTION
The LT3074 is a low voltage, ultralow noise, and ultrafast
transient response linear regulator with a PMBus serial
interface. The device supplies up to 3A with a typical
dropout voltage of 45mV. A 4.7µF reference bypass
capacitor decreases output voltage noise to 1.2μVRMS.
The wide bandwidth and high PSRR permit the use of
small ceramic capacitors, saving bulk capacitance and
cost. The LT3074 is supported by the LTPowerPlay
software development tool with a graphical user
interface (GUI).
The LT3074 sources a 100µA precision reference current
to the LT3074’s SETRES pin. Placing a resistor from this
SETRES pin to GND sets the output voltage. The
LT3074’s unity-gain operation provides virtually
constant output noise, PSRR, bandwidth and load
regulation, independent of the programmed output
voltage. Additionally, the LT3074 incorporates a unique
tracking feature (VIOC) to control the upstream
switching regulator to maintain a constant voltage
across the LT3074, and hence minimize power
dissipation.
The PMBus control allows to set the output current limit
from 1A to 6.4A in discrete steps of 0.05A. The PMBus
Telemetry feature provides information regarding the
output voltage and current, input voltage, bias voltage
and die temperature. The LT3074 features a CLKDIS pin
to control the internal clock. Pulling this pin to BIAS
disables the internal clocks to put LT3074 in the “quiet
mode”. The LT3074 is available in a compact 22 lead
(3mm × 4mm) LQFN package (laminate package with
QFN footprint).
SIMPLIFIED APPLICATION DIAGRAM
Figure 1. Simplified Application Diagram
Figure 2. Transient Response
10µF
0.47µF
MPWR
51kΩ
69.8kΩ
261kΩ
10kΩ
10kΩ
10kΩ
2.2µF
383kΩ
147kΩ
LT3074
BIAS
BIASDF
IN
OUT
SENSE
SETCAP
IMON
SDA
SCL
ALERT
ASEL
AGND
EN
VBIAS
2.375V TO 5.5V
VBIAS ≥ VOUT + 1.2V
VIN
VOUT + 0.1V TO 5.5V
VOUT
1.2V
10mA TO 3A
VIOC
PG
CLKDIS
POWER GOOD
SETRES
BIASAF
DGND
PGFB
22µF
4.7µF
12kΩ
COUT = 10µF
IOUT = 300mA TO 3A
3A/µs SLEW RATE
VOUT(NOMINAL) = 1V
VIN = 1.3V
VBIAS = 3.3V
5µs/DIV
IOUT
2A/DIV
VOUT
AC-COUPLED
20mV/DIV


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