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STM32F103C8T6 数据表(PDF) 57 Page - STMicroelectronics |
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STM32F103C8T6 数据表(HTML) 57 Page - STMicroelectronics |
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57 / 67 page  STM32F103xx Electrical characteristics 57/67 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 25 or Figure 26, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 25. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are available only on 100-pin packages. Figure 26. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF– inputs are available only on 100-pin packages. VREF+ (see note 1) STM32F103xx VDDA VSSA /VREF+ (see note 1) 1 µF // 10 nF 1 µF // 10 nF ai14388 VREF+/VDDA STM32F103xx 1 µF // 10 nF VREF–/VSSA ai14389 (See note 1) (See note 1) |
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