STM32F103C8T6 datasheet(38/67 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F103xx

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Wakeup time from low power mode

The wakeup times given in Table 21 is measured on a wakeup phase with a 8-MHz HSI RC

oscillator. The clock source used to wake up the device depends from the current operating

mode:

●

Stop or Standby mode: the clock source is the RC oscillator

●

Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and VDD supply

voltage conditions summarized in Table 7.

5.3.8

PLL characteristics

The parameters given in Table 22 are derived from tests performed under ambient

temperature and VDD supply voltage conditions summarized in Table 7.

Table 21.

Low-power mode wakeup timings(1)

TBD stands for to be determined.

Symbol

Parameter

Conditions

Typ

Max

Unit

tWUSLEEP

(2)

The wakeup time from Sleep and Stop mode are measured from the wakeup event to the point in which the

user application code reads the first instruction.

Wakeup from Sleep mode

Wakeup on HSI RC clock

0.75

TBD

µs

tWUSTOP

(2)

Wakeup from Stop mode

(regulator in run mode)

HSI RC wakeup time = 2 µs

TBD

µs

Wakeup from Stop mode

(regulator in low power mode)

HSI RC wakeup time = 2 µs,

Regulator wakeup from LP

mode time = 5 µs

7TBD

tWUSTDBY

(3)

The wakeup time from Standby mode is measured from the wakeup event to the point in which the device

exits from reset.

Wakeup from Standby mode

HSI RC wakeup time = 2 µs,

Regulator wakeup from power

down time = 38 µs

TBD

µs

Table 22.

PLL characteristics(1)

TBD stands for to be determined.

Symbol

Parameter

Test Conditions

Value

Unit

Min

Typ

Max(2)

Data based on device characterization, not tested in production.

fPLL_IN

PLL input clock

8.0

MHz

PLL input clock duty cycle

fPLL_OUT PLL multiplier output clock

MHz

fVCO

VCO frequency range

When PLL operates

(locked)

144

MHz

tLOCK

PLL lock time

200

µs

tJITTER

Cycle to cycle jitter (+/-3

peak to peak)

VDD is stable

TBD

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