CDCDB2000ENPPR datasheet(3/35 Pages) TI

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Table 4-1. Pin Functions

I/O TYPE(2)

DESCRIPTION

NAME(1)

NO.

INPUT CLOCK

CLKIN_P

LP-HCSL differential clock input. Typically connected directly to the differential

output of clock source.

CLKIN_N

OUTPUT CLOCKS

CK0_P

LP-HCSL differential clock output of channel 0. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect.

CK0_N

CK1_P

LP-HCSL differential clock output of channel 1. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect.

CK1_N

CK2_P

LP-HCSL differential clock output of channel 2. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect.

CK2_N

CK3_P

LP-HCSL differential clock output of channel 3. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect.

CK3_N

CK4_P

LP-HCSL differential clock output of channel 4. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect.

CK4_N

CK5_P

LP-HCSL differential clock output of channel 5. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect, and pin L8

(OE5# / DATA) is recommended to be either in DATA mode or pulled high.

CK5_N

M10

CK6_P

M11

LP-HCSL differential clock output of channel 6. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect, and pin L10

(OE6# / CLK) is recommended to be either in CLK mode or pulled high.

CK6_N

M12

CK7_P

L12

LP-HCSL differential clock output of channel 7. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect, and pin K11

(OE7#) is recommended to be pulled high to disable channel 7 output.

CK7_N

K12

CK8_P

J12

LP-HCSL differential clock output of channel 8. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect, and pin H11

(OE8#) is recommended to be pulled high to disable channel 8 output.

CK8_N

H12

CK9_P

G12

LP-HCSL differential clock output of channel 9. Typically connected directly to PCIe

differential clock input. If unused, the pins can be left no connect, and pin E12

(OE9#) is recommended to be pulled high to disable channel 9 output.

CK9_N

F12

CK10_P

D12

LP-HCSL differential clock output of channel 10. Typically connected directly to

PCIe differential clock input. If unused, the pins can be left no connect, and pin E11

(OE10# / SHFT_LD#) is recommended to be either in SHFT_LD# mode or pulled

high.

CK10_N

C12

CK11_P

B12

LP-HCSL differential clock output of channel 11. Typically connected directly to

PCIe differential clock input. If unused, the pins can be left no connect, and pin C11

(OE11#) is recommended to be pulled high to disable channel 11 output.

CK11_N

A12

CK12_P

A11

LP-HCSL differential clock output of channel 12. Typically connected directly to

PCIe differential clock input. If unused, the pins can be left no connect, and pin B10

(OE12#) is recommended to be pulled high to disable channel 12 output.

CK12_N

A10

CK13_P

LP-HCSL differential clock output of channel 13. Typically connected directly to