6 Detailed Description

6.1 Overview

The CDCDB2000 is a low additive-jitter, low propagation delay clock buffer designed to meet the strict

performance requirements for PCIe Gen 1-5, QPI and UPI reference clocks. The CDCDB2000 allows buffering

and replication of a single clock source to up to 20 individual outputs in the LP-HCSL format. The outputs of the

CDCDB2000 can be configured before they are enabled using the Side-Band control interface. The CDCDB2000

also includes status and control registers accessible by an SMBus version 2.0 compliant interface. The device

integrates a large amount of external passive components to reduce overall system cost.

6.2 Functional Block Diagram

CLKIN_P

CLKIN_N

SBEN

CK0_P

CK0_N

CK1_P

CK1_N

CK2_P

CK2_N

CK3_P

CK3_N

CK19_P

CK19_N

CLK

DATA

SHFT_LD#

SMBDAT

SMBCLK

Glitch

Free

Output

Control

Logic

Control

Logic

SADR0

SADR1

CKPWRGD_PD#

OE[12:5]#

S

B

I

SMB

/OE

6.3 Feature Description

6.3.1 Output Enable Control

The CDCDB2000 allows two methods to control the state of the output channels: SMBus/OE#, and Side-Band

Interface. Only one of the two methods can be active at any time, and the active interface is selected by the state

of the SBEN pin. Both methods of output control can assign the state of each output individually.

When in SMBus/OE# control is selected, the OE# pins become active. The OE# pins control the state of the

output with the same number. For example, the OE5# pin controls the state of the CK5 output driver. The SMBus

registers may enable/disable the output regardless of the OE# pin state if desired.

6.3.2 SMBus

The CDCDB2000 has an SMBus interface that is active only when CKPWRGD_PD# = 1.The SMBus allows

individual enable/disable of each output when the SMBus mode is selected using the SBEN pin.

When CKPWRGD_PD# = 0, the SMBus pins are placed in a Hi-Z state, but all register settings are retained. The

SMBus register values are only retained while VDD_A remains inside of the recommended operating voltage.

6.3.2.1 SMBus Address Assignment

The SMBus address is assigned by configuration of two pins (SADR1 and SADR0) that each support three

levels. This configuration allows the CDCDB2000 to assume 9 different SMBus addresses.

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CDCDB2000

SNAS787B – NOVEMBER 2019 – REVISED OCTOBER 2024

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Product Folder Links: CDCDB2000