CDCDB2000ENPPR datasheet(4/35 Pages) TI

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Table 4-1. Pin Functions (continued)

I/O TYPE(2)

DESCRIPTION

NAME(1)

NO.

CK18_P

LP-HCSL differential clock output of channel 18. Typically connected directly to

PCIe differential clock input. If unused, the pins can be left no connect.

CK18_N

CK19_P

LP-HCSL differential clock output of channel 19. Typically connected directly to

PCIe differential clock input. If unused, the pins can be left no connect.

CK19_N

MANAGEMENT AND CONTROL

CKPWRGD_PD#

I, PD

Clock Power Good and Power Down multi-function input pin with internal 120-kΩ

pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can be

left no connect. On first high transition, PWRGD samples the latched SADR[1:0]

inputs and starts up device. After PWRGD has been asserted high for the first time,

the pin becomes a PD# pin and it controls power-down mode:

LOW: Power-down mode, all output channels tri-stated.

HIGH: Normal operation mode.

OE5#

DATA

I, PD

Output enable for channel 5 and Side-Band Interface data multi-function pin with

internal 120-kΩ pulldown. Typically connected to GPIO of microcontroller. If both

modes are unused, the pin can be left no connect. When pin E2 = LOW, OE5#

mode. Output enable for channel 5, active low.

LOW: enable output channel 5.

HIGH: disable output channel 5. When pin E2 = HIGH, DATA mode. Side-Band

Interface data pin.

OE6#

CLK

L10

I, PD

Output enable for channel 6 and Side-Band Interface clock multi-function pin with

internal 120-kΩ pulldown. Typically connected to GPIO of microcontroller. If both

modes are unused, the pin can be left no connect. When pin E2 = LOW, OE6#

mode. Output Enable for channel 6, active low.

LOW: enable output channel 6.

HIGH: disable output channel 6. When pin E2 = HIGH, CLK mode. Side-Band

interface clock pin.

OE7#

K11

I, PD

Output Enable for channel 7 with internal 120-kΩ pulldown, active low. Typically

connected to GPIO of microcontroller. If unused, the pin can be left no connect.

LOW: enable output channel 7.

HIGH: disable output channel 7.

OE8#

H11

I, PD

Output Enable for channel 8, with internal 120-kΩ pulldown, active low. Typically

connected to GPIO of microcontroller. If unused, the pin can be left no connect.

LOW: enable output channel 8.

HIGH: disable output channel 8.

OE9#

E12

I, PD

Output Enable for channel 9, with internal 120-kΩ pulldown, active low. Typically

connected to GPIO of microcontroller. If unused, the pin can be left no connect.

LOW: enable output channel 9.

HIGH: disable output channel 9.

OE10#

SHFT_LD#

E11

I, PD

Output enable for channel 10 and Side-Band Interface load shift registers multi-

function pin with internal 120-kΩ pulldown. Typically connected to GPIO of

microcontroller. If both modes are unused, the pin can be left no connect. When pin

E2 = LOW, OE10# mode. Output Enable for channel 10, active low.

LOW: enable output channel 10.

HIGH: disable output channel 10. When pin E2 = HIGH, SHFT_LD# mode. Side-

Band Interface load shift registers pin.

LOW: disable Side-Band Interface shift register.

HIGH: enable Side-Band Interface shift register.

A falling edge transfers the Side-Band shift register contents to the output register.

OE11#

C11

I, PD

Output Enable for channel 11 with internal 120-kΩ pulldown, active low. Typically

connected to GPIO of microcontroller. If unused, the pin can be left no connect.

LOW: enable output channel 11.

HIGH: disable output channel 11.

OE12#

B10

I, PD

Output Enable for channel 12 with internal 120-kΩ pulldown, active low. Typically

connected to GPIO of microcontroller. If unused, the pin can be left no connect.

LOW: enable output channel 12.

HIGH: disable output channel 12.

CDCDB2000

SNAS787B – NOVEMBER 2019 – REVISED OCTOBER 2024

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