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AD8317 数据表(PDF) 4 Page - Analog Devices

部件名 AD8317
功能描述  0.1 GHz to 2.5 GHz 70 dB Logarithmic Detector/Controller
PDF  23 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD8317 数据表(HTML) 4 Page - Analog Devices

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Data Sheet
AD8313
SPECIFICATIONS
analog.com
Rev. F | 4 of 23
Table 2. (Continued)
Parameter
Test Conditions/Comments
Min1
Typ
Max1
Unit
2.5 GHz6
Nominal conditions
±3 dB Dynamic Range
48
66
dB
Range Center
–34
dBm
±1 dB Dynamic Range
46
dB
Slope
16
20
25
mV/dB
Intercept
–111
–92
–72
dBm
2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
47
68
dB
Range Center
–34.5
dBm
±1 dB Dynamic Range
46
dB
Slope
14.5
20
25
mV/dB
Intercept
–128
–92
–56
dBm
Temperature Sensitivity
PIN =–10 dBm
–0.040
dB/°C
3.5 GHz4
Nominal conditions
±3 dB Dynamic Range
43
dB
±1 dB Dynamic Range
35
dB
Slope
24
mV/dB
Intercept
–65
dBm
CONTROL MODE
Controller Sensitivity
f = 900 MHz
23
V/dB
Low Frequency Gain
VSET to VOUT7
84
dB
Open-Loop Corner Frequency
VSET to VOUT7
700
Hz
Open-Loop Slew Rate
f = 900 MHz
2.5
V/µs
VSET Delay Time
150
ns
VOUT INTERFACE
Current Drive Capability
Source Current
400
µA
Sink Current
10
mA
Minimum Output Voltage
Open-loop
50
mV
Maximum Output Voltage
Open-loop
VPOS – 0.1
V
Output Noise Spectral Density
PIN = –60 dBm, fSPOT = 100 Hz
2.0
µV/√Hz
PIN = –60 dBm, fSPOT = 10 MHz
1.3
µV/√Hz
Small Signal Response Time
PIN = –60 dBm to –57 dBm, 10% to 90%
40
60
ns
Large Signal Response Time
PIN = No signal to 0 dBm; settled to 0.5 dB
110
160
ns
VSET INTERFACE
Input Voltage Range
0
VPOS
V
Input Impedance
18||1
kΩ||pF3
POWER-DOWN INTERFACE
PWDN Threshold
VPOS/2
V
Power-Up Response Time
Time delay following high to low transition until device
meets full specifications.
1.8
µs
PWDN Input Bias Current
PWDN = 0 V
5
µA
PWDN = VS
<1
µA
POWER SUPPLY
Operating Range
2.7
5.5
V
Powered-Up Current
13.7
15.5
mA
4.5 V ≤VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C
18.5
mA
2.7 V ≤VS ≤ 3.3 V, –40°C ≤ T ≤ +85°C
18.5
mA



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