Data Sheet

AD8313

INTERFACES

analog.com

Rev. F | 13 of 23

This section describes the signal and control interfaces and their

behavior. On-chip resistances and capacitances exhibit variations

of up to ±20%. These resistances are sometimes temperature-de-

pendent, and the capacitances may be voltage-dependent.

POWER-DOWN INTERFACE, PWDN

The power-down threshold is accurately centered at the midpoint of

the supply as shown in Figure 24. If Pin 5 is left unconnected or

tied to the supply voltage (recommended), the bias enable current

is shut off, and the current drawn from the supply is predominately

through a nominal 300 kΩ chain (20 µA at 3 V). When grounded,

the bias system is turned on. The threshold level is accurately at

VPOS/2. When operating in the device ON state, the input bias

current at the PWDN pin is approximately 5 µA for VPOS = 3 V.

Figure 24. Power-Down Threshold Circuitry

SIGNAL INPUTS, INHI, INLO

The simplest low frequency ac model for this interface consists

of just a 900 Ω resistance, RIN, in shunt with a 1.1 pF input capac-

itance, CIN, connected across INHI and INLO. Figure 25 shows

these distributed in the context of a more complete schematic. The

input bias voltage shown is for the enabled chip; when disabled,

it rises by a few hundred millivolts. If the input is coupled via

capacitors, this change may cause a low level signal transient to

be introduced, having a time constant formed by these capacitors

and RIN. For this reason, large coupling capacitors should be well

matched. This is not necessary when using the small capacitors

found in many impedance transforming networks used at high

frequencies.

Figure 25. Input Interface Simplified Schematic

For high frequency use, Figure 26 shows the input impedance

plotted on a Smith chart. This measured result of a typical device

includes a 191 mil 50 Ω trace and a 680 pF capacitor to ground

from the INLO pin.

Figure 26. Typical Input Impedance

LOGARITHMIC/ERROR OUTPUT, VOUT

The rail-to-rail output interface is shown in Figure 27. VOUT can

run from within about 50 mV of ground, to within about 100 mV

of the supply voltage, and is short-circuit safe to either supply.

However, the sourcing load current, ISOURCE, is limited to that which

is provided by the PNP transistor, typically 400 µA. Larger load

currents can be provided by adding an external NPN transistor (see

the Applications Information section). The dc open-loop gain of this

amplifier is high, and it may be regarded as an integrator having

a capacitance of 2 pF (CINT) driven by the current-mode signal

generated by the summed outputs of the nine detector stages,

which is scaled approximately 4.0 µA/dB.

Figure 27. Output Interface Circuitry

Thus, for midscale RF input of about 3 mV, which is some 40 dB

above the minimum detector output, this current is 160 µA, and the

output changes by 8 V/µs. When VOUT is connected to VSET, the

rise and fall times are approximately 40 ns (for RL ≥ 10 kΩ).

The nominal slew rate is 2.5 V/µs. The HF compensation technique

results in stable operation with a large capacitive load, CL, though

the positive-going slew rate is then limited by ISOURCE/CL to 1 V/µs

for CL = 400 pF.

SETPOINT INTERFACE, VSET

The setpoint interface is shown in Figure 28. The voltage, VSET,

is divided by a factor of 3 in a resistive attenuator of 18 kΩ total

resistance. The signal is converted to a current by the action of the

op amp and the resistor R3 (1.5 kΩ), which balances the current

generated by the summed output of the nine detector cells at the