Data Sheet

AD8313

APPLICATIONS INFORMATION

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Rev. F | 15 of 23

BASIC CONNECTIONS FOR LOG (RSSI) MODE

Figure 29 shows the AD8313 connected in its basic measurement

mode. A power supply between 2.7 V and 5.5 V is required. The

power supply to each of the VPOS pins should be decoupled with a

0.1 µF surface-mount ceramic capacitor and a 10 Ω series resistor.

The PWDN pin is shown as grounded. The AD8313 may be disa-

bled by a logic high at this pin. When disabled, the chip current is

reduced to about 20 µA from its normal value of 13.7 mA. The logic

threshold is at VPOS/2, and the enable function occurs in about 1.8

µs. However, that additional settling time is generally needed at low

input levels. While the input in this case is terminated with a simple

50 Ω broadband resistive match, there are many ways in which the

input termination can be accomplished. These are discussed in the

Input Coupling section.

VSET is connected to VOUT to establish a feedback path that

controls the overall scaling of the logarithmic amplifier. The load

resistance, RL, should not be lower than 5 kΩ so that the full-scale

output of 1.75 V can be generated with the limited available current

of 400 µA max.

As stated in the Absolute Maximum Ratings table, an externally

applied overvoltage on the VOUT pin, which is outside the range 0

V to VPOS, is sufficient to cause permanent damage to the device.

If overvoltages are expected on the VOUT pin, a series resistor,

RPROT, should be included as shown. A 500 Ω resistor is sufficient

to protect against overvoltage up to ±5 V; 1000 Ω should be used if

an overvoltage of up to ±15 V is expected. Since the output stage is

meant to drive loads of no more than 400 µA, this resistor does not

impact device performance for higher impedance drive applications

(higher output current applications are discussed in the Increasing

Output Current section).

Figure 29. Basic Connections for Log (RSSI) Mode

OPERATING IN CONTROLLER MODE

Figure 30 shows the basic connections for operation in controller

mode. The link between VOUT and VSET is broken and a setpoint

is applied to VSET. Any difference between VSET and the equivalent

input power to the AD8313 drives VOUT either to the supply rail or

close to ground. If VSET is greater than the equivalent input power,

VOUT is driven toward ground, and vice versa.

Figure 30. Basic Connections for Operation in the Controller Mode

This mode of operation is useful in applications where the output

power of an RF power amplifier (PA) is to be controlled by an

analog AGC loop (Figure 31). In this mode, a setpoint voltage, pro-

portional in dB to the desired output power, is applied to the VSET

pin. A sample of the output power from the PA, via a directional

coupler or other means, is fed to the input of the AD8313.

Figure 31. Setpoint Controller Operation

VOUT is applied to the gain control terminal of the power amplifier.

The gain control transfer function of the power amplifier should be

an inverse relationship, that is, increasing voltage decreases gain.

A positive input step on VSET (indicating a demand for increased

power from the PA) drives VOUT toward ground. This should be

arranged to increase the gain of the PA. The loop settles when

VOUT settles to a voltage that sets the input power to the AD8313 to

the dB equivalent of VSET.

INPUT COUPLING

The signal can be coupled to the AD8313 in a variety of ways. In all

cases, there must not be a dc path from the input pins to ground.

Some of the possibilities include dual-input coupling capacitors, a

flux-linked transformer, a printed circuit balun, direct drive from a

directional coupler, or a narrow-band impedance matching network.

Figure 32 shows a simple broadband resistive match. A termination

resistor of 53.6 Ω combines with the internal input impedance

of the AD8313 to give an overall resistive input impedance of

approximately 50 Ω. It is preferable to place the termination resistor

directly across the input pins, INHI to INLO, where it lowers the

possible deleterious effects of dc offset voltages on the low end of

the dynamic range. At low frequencies, this may not be quite as