Data Sheet

AD8313

APPLICATIONS INFORMATION

analog.com

Rev. F | 17 of 23

therefore,

L

2= 1ω2CIN=2.3 μH

(10)

Figure 36. Input Matching Example

With CIN and L2 temporarily out of the picture, the focus is now on

matching a 50 Ω source resistance to a (purely resistive) load of

900 Ω and calculating values for CMATCH and L1. When

RSRIN= L1CMATCH

(11)

the input looks purely resistive at a frequency given by

f0

= 1

2π L1×CMATCH

=100 MHz

(12)

Solving for CMATCH gives

CMATCH= 1RSRIN× 12πf0=7.5 pF

(13)

Solving for L1 gives

L

1= RSRIN2πf0=337.6 nH

(14)

Because L1 and L2 are parallel, they can be combined to give the

final value for LMATCH, that is,

LMATCH=L1×L2L1+L2=294 nH

(15)

C1 and C2 can be chosen in a number of ways. First, C2 can be

set to a large value, for example, 1000 pF, so that it appears as

an RF short. C1 would then be set equal to the calculated value of

CMATCH. Alternatively, C1 and C2 can each be set to twice CMATCH

so that the total series capacitance is equal to CMATCH. By making

C1 and C2 slightly unequal (that is, select C2 to be about 10% less

than C1) but keeping their series value the same, the amplitude of

the signals on INHI and INLO can be equalized so that the AD8313

is driven in a more balanced manner. Any of the options detailed

above can be used provided that the combined series value of C1

and C2, that is, C1 × C2/(C1 + C2) is equal to CMATCH.

In all cases, the values of CMATCH and LMATCH must be chosen from

standard values. At this point, these values need now be installed

on the board and measured for performance at 100 MHz. Because

of board and layout parasitics, the component values from the

preceding example had to be tuned to the final values of CMATCH =

8.9 pF and LMATCH = 270 nH as shown in Table 5.

Assuming a lossless matching network and noting conservation of

power, the impedance transformation from RS to RIN (50 Ω to 900

Ω) has an associated voltage gain given by

Gain dB=20×log RINRS=12.6 dB

(16)

Because the AD8313 input responds to voltage and not to true

power, the voltage gain of the matching network increases the

effective input low-end power sensitivity by this amount. Thus, in

this case, the dynamic range is shifted downward, that is, the 12.6

dB voltage gain shifts the 0 dBm to −65 dBm input range downward

to −12.6 dBm to −77.6 dBm. However, because of network losses,

this gain is not be fully realized in practice. Refer to Figure 33 and

Figure 34 for an example of practical attainable voltage gains.

Table 5 shows recommended values for the inductor and capacitors

in Figure 35 for some selected RF frequencies in addition to the

associated theoretical voltage gain. These values for a reactive

match are optimal for the board layout detailed as Figure 45.

As previously discussed, a modification of the board layout produ-

ces networks that may not perform as specified. At 2.5 GHz,

a shunt inductor is sufficient to achieve proper matching. Conse-

quently, C1 and C2 are set sufficiently high that they appear as RF

shorts.

Table 5. Recommended Values for C1, C2, and LMATCH in Figure 35

Freq.

(MHz)

CMATCH

(pF)

C1

(pF)

C2

(pF)

LMATCH

(nH)

Voltage

Gain (dB)

100

8.9

22

15

270

12.6

1000

270

900

1.5

3

3

8.2

9.0

1.5

1000

8.2

1900

1.5

3

3

2.2

6.2

1.5

1000

2.2

2500

Large

390

390

2.2

3.2

Figure 37 shows the voltage response of the 100 MHz matching

network. Note the high attenuation at lower frequencies typical of a

high-pass network.