Data Sheet

AD8313

CIRCUIT DESCRIPTION

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Rev. F | 11 of 23

The AD8313 is an 8-stage logarithmic amplifier, specifically de-

signed for use in RF measurement and power amplifier control

applications at frequencies up to 2.5 GHz. A block diagram is

shown in Figure 22. For a detailed description of log amp theory

and design principles, refer to the AD8307 data sheet.

Figure 22. Block Diagram

A fully differential design is used. Inputs INHI and INLO (Pins 2 and

3) are internally biased to approximately 0.75 V below the supply

voltage, and present a low frequency impedance of nominally 900

Ω in parallel with 1.1 pF. The noise spectral density referred to the

input is 0.6 nV/√Hz, equivalent to a voltage of 35 V rms in a 3.5

GHz bandwidth, or a noise power of −76 dBm re: 50 Ω. This sets

the lower limit to the dynamic range; the Applications Information

section shows how to increase the sensitivity by using a matching

network or input transformer. However, the low end accuracy of

the AD8313 is enhanced by specially shaping the demodulation

transfer characteristic to partially compensate for errors due to

internal noise.

Each of the eight cascaded stages has a nominal voltage gain

of 8 dB and a bandwidth of 3.5 GHz. Each stage is supported

by precision biasing cells that determine this gain and stabilize

it against supply and temperature variations. Since these stages

are direct-coupled and the dc gain is high, an offset compensation

loop is included. The first four stages and the biasing system

are powered from Pin 4, while the later stages and the output

interfaces are powered from Pin 1. The biasing is controlled by a

logic interface PWDN (Pin 5); this is grounded for normal operation,

but may be taken high (to VS) to disable the chip. The threshold is

at VPOS/2 and the biasing functions are enabled and disabled within

1.8 µs.

Each amplifier stage has a detector cell associated with its output.

These nonlinear cells perform an absolute value (full-wave rectifica-

tion) function on the differential voltages along this backbone in a

transconductance fashion; their outputs are in current-mode form

and are thus easily summed. A ninth detector cell is added at the

input of the AD8313. Since the midrange response of each of these

nine detector stages is separated by 8 dB, the overall dynamic

range is about 72 dB (Figure 23). The upper end of this range is

determined by the capacity of the first detector cell, and occurs at

approximately 0 dBm. The practical dynamic range is over 70 dB

to the ±3 dB error points. However, some erosion of this range can

occur at temperature and frequency extremes. Useful operation to

over 3 GHz is possible, and the AD8313 remains serviceable at 10

MHz, needing only a small amount of additional ripple filtering.

Figure 23. Typical RSSI Response and Error vs. Input Power at 1.9 GHz

The fluctuating current output generated by the detector cells, with

a fundamental component at twice the signal frequency, is filtered

first by a low-pass section inside each cell, and then by the output

stage. The output stage converts these currents to a voltage, VOUT,

at VOUT (Pin 8), which can swing rail-to-rail. The filter exhibits

a 2-pole response with a corner at approximately 12 MHz and

full-scale rise time (10% to 90%) of 40 ns. The residual output ripple

at an input frequency of 100 MHz has an amplitude of under 1 mV.

The output can drive a small resistive load; it can source currents

of up to 400 µA, and sink up to 10 mA. The output is stable with

any capacitive load, though settling time could be impaired. The low

frequency incremental output impedance is approximately 0.2 Ω.

In addition to its use as an RF power measurement device (that

is, as a logarithmic amplifier), the AD8313 may also be used in

controller applications by breaking the feedback path from VOUT to

VSET (Pin 7), which determines the slope of the output (nominally

18 mV/dB). This pin becomes the setpoint input in controller modes.

In this mode, the voltage VOUT remains close to ground (typically

under 50 mV) until the decibel equivalent of the voltage VSET

is reached at the input, when VOUT makes a rapid transition to

a voltage close to VPOS (see the Operating in Controller Mode

section). The logarithmic intercept is nominally positioned at −100

dBm (re: 50 Ω); this is effective in both the log amp mode and the

controller mode.

With Pins 7 and 8 connected (log amp mode), the output can be

stated as

VOUT = VSLOPE (PIN + 100 dBm)

(1)

where PIN is the input power stated in dBm when the source

is directly terminated in 50 Ω. However, the input impedance of

the AD8313 is much higher than 50 Ω, and the sensitivity of this

device may be increased by about 12 dB by using some type

of matching network (see below), which adds a voltage gain and