ADP1828

Rev. 0 | Page 8 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

SYNC

EN

IN

COMP

GND

VREG

FREQ

CLKSET

BST

DH

PGND

CSL

SW

SS

TRK

FB

PGOOD

PV

DL

CLKOUT

TOP VIEW

(Not to Scale)

ADP1828

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin

No.

Mnemonic

Description

1

FREQ

Frequency Control Input. Low for 300 kHz, high for 600 kHz, or connect a resistor from FREQ to GND to set the free-

running frequency between 300 kHz and 600 kHz.

2

SYNC

Frequency Synchronization Input. Accepts external signals between 300 kHz and 600 kHz if FREQ is set to low, or

is less than 6 V.

3

EN

Enable Input. Drive EN high or tristate EN to turn on the ADP1828 controller, and drive it low to turn off. Connect EN to

IN for automatic startup.

4

IN

Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 18 V to power the ADP1828 from LDO, VREG; tie PV

to VREG. For input voltages between 3 V and 5.5 V, tie IN, PV, and VREG together.

5

VREG

Output of the Internal Linear Regulator (LDO). The internal circuitry and gate drivers are powered from VREG. Bypass

VREG to AGND plane with 1 μF ceramic capacitor for stable operation, for example, a 10 V X5R 1 μF ceramic capacitor

is sufficient. The VREG output is 5 V when IN = 5 V + dropout. Connect IN to VREG and PV when IN = 3 V to 5.5 V. For

applications with IN < 5.5 V and IN not connected to VREG, keep in mind that VREG = VIN – dropout. VREG needs to be

≥3 V for proper operation.

6

GND

Ground for Internal Circuits. Tie the bottom of the feedback dividers to this GND.

7

COMP

Error Amplifier Output. Connect an RC network from COMP to FB for loop compensation.

8

FB

Voltage Feedback. Connect a resistor divider from the buck regulator output to GND and tie the tap to FB to set the

output voltage.

9

TRK

Tracking Input. To track a master voltage, drive TRK from a voltage divider from the master voltage. If the tracking

function is not used, connect TRK to VREG.

10

SS

Soft Start Control Input. Connect a capacitor from SS to GND to set the soft start period.

11

PGOOD

Open-Drain Power-Good Output. Sinks current when FB is out of regulation. Connect a pull-up resistor from

PGOOD to VREG.

12

PV

Positive Input Voltage for Gate Driver DL. When IN is 3 V to 5.5 V, connect IN to VREG and PV. Connect a 1 μF bypass

capacitor from PV to PGND. When IN = 5.5 V to 18 V, connect PV to VREG.

13

DL

Low-Side (Synchronous Rectifier) Gate Driver Output.

14

PGND

Power GND. Ground for gate driver.

15

CSL

Current Sense Comparator Inverting Input. Connect a resistor between CSL and SW to set the current-limit offset.

16

SW

Switch Node Connection.

17

DH

High-Side (Switch) Gate Driver Output.

18

BST

Boost Capacitor Input. Powers the high-side gate driver DH. Connect a 0.22 μF to 0.47 μF ceramic capacitor from BST

to SW and a Schottky diode from PV to BST.

19

CLKSET

Clock Set Input. Setting CLKSET to Logic high (connect CLKSET to VREG) sets the CLKOUT to 2× the internal oscillator

frequency and is in phase with the oscillator. Setting CLKSET to Logic low sets the CLKOUT to 1× the oscillator

frequency and 180° out of phase.

20

CLKOUT

able to drive a 100 pF load.