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ADP1828YRQZ-R7 数据表(PDF) 26 Page - Analog Devices |
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ADP1828YRQZ-R7 数据表(HTML) 26 Page - Analog Devices |
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26 / 32 page  ADP1828 Rev. 0 | Page 26 of 32 A more accurate solution is to provide a divider from the master voltage that sets the TRK pin voltage to be something lower than 0.6 V at regulation, for example, 0.5 V. The slave channel can be viewed as having a 0.5 V external reference supplied by the master voltage. Keep in mind that PGOOD is tripped when the TRK voltage is set to less than 0.55 V. Once this is complete, the FB divider for the slave voltage is designed as in the Compensating the Voltage Mode Buck Regulator section except to substitute the 0.5 V reference for the VFB voltage. The ratio of the slave output voltage to the master voltage is a function of the two dividers: ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + = TRKB TRKT BOT TOP MASTER OUT R R R R V V 1 1 (51) Figure 46 shows an example of ratiometric tracking circuit and Figure 47 shows its voltage tracking waveforms. FB TRK SS RTRKB 10kΩ RTRKT 49.9kΩ 0.55V ADP1828 OR ADP1829 FB ADP1828 EN EN SS RTOP 22.6kΩ RBOT 10kΩ CSS 1µF CSS 150nF 3.3V VOUT_MASTER 1.8V VOUT_SLAVE Figure 46. An Example of a Ratiometric Tracking Circuit CH1 5.00V CH3 1.00V CH2 1.00V M 100ms A CH1 2.60V 1 4 CH4 1.00V VOUT_MASTER EN FOR BOTH ADP1828 VOUT_SLAVE TRK_SLAVE BW BW BW Figure 47. Ratiometric Tracking of Figure 46 Another option is to add another tap to the divider for the master voltage. Split the RBOT resistor of the master voltage into two pieces, with the new tap at 0.5 V when the master voltage is in regulation. This saves one resistor, but be aware that Type III compensation on the master voltage causes the feedforward signal of the master voltage to appear at the TRK input of the slave channel. Figure 48 shows an example of DDR memory termination application circuit, where the DDR memory termination voltage, VTT, is ½ of VDDQ. VTT can sink current during the off cycle of the ADP1828. The output waveform in Figure 49 shows that VTT changes by one-half of the output change in VDDQ. FB TRK SS RTRKB 10kΩ RTRKT 40.2kΩ 0.5V ADP1828 OR ADP1829 FB ADP1828 EN EN SS RTOP 15kΩ RBOT 10kΩ CSS 1µF CSS 150nF 2.5V VDDQ 1.25V VTT Figure 48. An Example of a DDR Termination Circuit CH1 500mV CH3 500mV CH2 100mV M 200µs A CH1 50.0mV 3 2 1 VDDQ (2.5V ± 0.25V, AC-COUPLED) VTT (1.25V ± 0.125V, AC-COUPLED) TRK BW BW BW T Figure 49. DDR Termination; Output Waveforms of Figure 48 In addition, by selecting the resistor values in the divider carefully, Equation 51 shows that the slave voltage output can be made to have a faster ramp rate than that of the master voltage by setting the TRK voltage at the slave larger than 0.6 V and RTRKB greater than RTRKT. Make sure that the master SS period is long enough (that is, use a sufficiently large SS capacitor) such that the input inrush current does not run into the current limit of the power supply during startup. CH1 5.00V CH3 1.00V CH2 1.00V M 100ms A CH1 2.60V 1 4 CH4 1.00V VOUT_MASTER EN FOR BOTH ADP1828 TRK_SLAVE BW BW BW VOUT_SLAVE Figure 50. Ratiometric Tracking of Figure 46 with RTRKT = 5 kΩ |
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