ADP1828YRQZ-R7 datasheet(21/32 Pages) AD

21 / 32 page

ADP1828

Rev. 0 | Page 21 of 32

Depending on component selection, one zero might already be

generated by the ESR of the output capacitor. Calculate this zero

corner frequency, fESR, as

OUT

ESR

(18)

Figure 36 shows a typical Bode plot of the LC filter by itself.

The gain of the LC filter at crossover can be linearly

approximated from Figure 36 as

ESR

FILTER

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

ESR

FILTER

log

(19)

fESR ≈ fCO, then add another 3 dB to account for the local

difference between the exact solution and the linear approxi-

mation in Equation 19.

0dB

GAIN

FREQUENCY

PHASE

fLC

fESR

fCO

fSW

AFILTER

–40dB/dec

ΦFILTER

0°

–90°

–180°

–20dB/dec

Figure 36. LC Filter Bode Plot

To compensate the control loop, the gain of the system must

be brought back up so that it is 0 dB at the desired crossover

frequency. Some gain is provided by the PWM modulation itself.

⎟

⎠

⎞

⎜

⎝

⎛

RAMP

MOD

log

(20)

For systems using the internal oscillator, this becomes

⎟

⎠

⎞

⎜

⎝

⎛

log

MOD

(21)

Note that if the converter is being synchronized, the ramp

voltage, VRAMP, is lower than 1.0 V by the percentage of

frequency increase over the nominal setting of the FREQ pin:

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

SYNC

FREQ

RAMP

(22)

For example, if FREQ is grounded or connected to VREG, then

fFREQ is 300 kHz or 600 kHz, respectively. If the frequency is set

by a resistor, then fFREQ is 300 kHz and fSYNC is the frequency set

by the resistor. VRAMP is greater than 1.0 V if fSYNC is less than

fFREQ. The rest of the system gain needs to reach 0 dB at cross-

over. The total gain of the system, therefore, is given by

AT = AMOD + AFILTER + ACOMP

(23)

where:

AMOD is the gain of the PWM modulator.

AFILTER is the gain of the LC filter including the effects of

the ESR zero.

ACOMP is the gain of the compensated error amplifier.

Additionally, the phase of the system must be brought back

up to guarantee stability. Note from the Bode plot of the filter

that the LC contributes −180° of phase shift (see Figure 36).

Because the error amplifier is an integrator at low frequency,

it contributes an initial −90°. Therefore, before adding com-

pensation or accounting for the ESR zero, the system is already

down −270°. To avoid loop inversion at crossover, or −180°

phase shift, a good initial practical design is to require a phase

margin of 60°, which is therefore an overall phase loss of −120°

from the initial low frequency dc phase. The goal of the com-

pensation is to boost the phase back up from −270° to −120°

at crossover.

Two common compensation schemes are used, which are

sometimes referred to as Type II or Type III compensation,

depending on whether the compensation design includes

two or three poles (see the Type II Compensator and Type III

Compensator sections). Dominant-pole compensation, or

single-pole compensation, is referred to as Type I compensation,

but it is not very useful for dealing successfully with switching

regulators.

If the zero produced by the ESR of the output capacitor provides

sufficient phase boost at crossover, Type II compensation is

adequate. If the phase boost produced by the ESR of the output

capacitor is not sufficient, another zero is added to the compen-

sation network, and thus Type III is used.

In Figure 37, the location of the ESR zero corner frequency

gives a significantly different net phase at the crossover

frequency.

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