ADP1828YRQZ-R7 datasheet(15/32 Pages) AD

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ADP1828

Rev. 0 | Page 15 of 32

If the output voltage is precharged prior to turn-on, the ADP1828

prevents reverse inductor current, which would discharge the

output capacitor. Once the voltage at SS exceeds the regulation

voltage (typically 0.6 V), the reverse current is re-enabled to

allow the output voltage regulation to be independent of load

current.

When a controller is disabled or experiences any form of fault

condition, the soft start capacitor is discharged through an

internal 6 kΩ resistor, so that at restart or recovery from fault

the output voltage soft starts again.

ERROR AMPLIFIER

The ADP1828 error amplifier is an operational amplifier. The

ADP1828 senses the output voltage through an external resistor

divider at the FB pin. The FB pin is the inverting input to the

error amplifier. The error amplifier compares this feedback

voltage to the internal 0.6 V reference, and the output of the

error amplifier appears at the COMP pin. The COMP pin

voltage then directly controls the duty cycle of the switching

converter.

A series/parallel RC network is tied between the FB pin and the

COMP pin to provide the compensation for the buck converter

control loop. A detailed design procedure for compensating the

system is provided in the Compensating the Voltage Mode Buck

Regulator section.

The error amplifier output is clamped between a lower limit of

about 0.75 V and a higher limit of up to about 3.6 V, depending

on the VREG voltage. When the COMP pin is low, the switching

duty cycle goes to 0%, and when the COMP pin is high, the

switching duty cycle goes to the maximum.

The SS and TRK pins are auxiliary positive inputs to the error

amplifier. Whichever voltage is lowest (SS, TRK, or the internal

0.6 V reference) controls the FB pin voltage and the output. As

a consequence, if two of these inputs are close to each other, a

small offset is imposed on the error amplifier.

CURRENT-LIMIT SCHEME

The ADP1828 employs a programmable, cycle-by-cycle lossless

current-limit circuit that uses an inexpensive resistor to set the

threshold. Every switching cycle, the synchronous rectifier

turns on for a minimum time and the voltage drop across

the MOSFET RDSON is measured to determine if the current

is too high.

This measurement is done by an internal current-limit compa-

rator and an external current-limit setting resistor. The resistor

is connected between the switch node (that is the drain of the

rectifier MOSFET) and the CSL pin. The CSL pin, which is the

inverting input of the comparator, forces 50 μA through the

resistor to create an offset voltage drop across it.

When the inductor current is flowing in the MOSFET rectifier,

its drain is forced below PGND by the voltage drop across its

RDSON. If the RDSON voltage drop exceeds the preset drop on

the current-limit resistor, the inverting comparator input is

similarly forced below PGND and an overcurrent fault is

flagged.

The normal transient ringing on the switch node is ignored

for 100 ns after the synchronous rectifier turns on, so the over-

current condition must also persist for 100 ns for a fault to be

flagged.

When the ADP1828 senses an overcurrent condition, the next

switching cycle is suppressed, the soft start capacitor is discharged

through an internal 6 kΩ resistor, and the error amplifier output

voltage is pulled down. The ADP1828 remains in this mode for

as long as the overcurrent condition persists.

Note that the current-limit scheme in the ADP1828 is not the

same as a short-circuit protection. The ADP1828 does not go

into current foldback in the event of a short circuit. The short-

circuit output current is the current limit set by the RCL resistor

and is monitored cycle by cycle. When the overcurrent condition

is removed, operation resumes in soft start mode.

MOSFET DRIVERS

The DH pin drives the high-side switch MOSFET. This is a

boosted 5 V gate driver that is powered by a bootstrap capacitor

circuit. This configuration allows the high-side, N-channel

MOSFET gate to be driven above the input voltage, allowing

full enhancement and a low voltage drop across the MOSFET.

The bootstrap capacitor is connected from the SW pin to the

BST pin. A bootstrap Schottky diode connected from the PV

pin to the BST pin recharges the boost capacitor every time the

SW node goes low. Use a bootstrap capacitor value greater than

100× the high-side MOSFET input capacitance.

In practice, the switch node can run up to 24 V of input voltage,

and the boost nodes can operate more than 5 V above this to

allow full gate drive. The IN pin can be run from 3 V to 18 V.

The switching cycle is initiated by the internal clock signal. The

high-side MOSFET is turned on by the DH driver, and the SW

node goes high, pulling up on the inductor. When the internally

generated ramp signal crosses the COMP pin voltage, the switch

MOSFET is turned off and the low-side synchronous rectifier

MOSFET is turned on by the DL driver. Active break-before-

make circuitry as well as a supplemental fixed dead time are

used to prevent cross-conduction in the switches.

The DL pin provides the gate drive for the low-side MOSFET

synchronous rectifier. Internal circuitry monitors the external

MOSFETs to ensure break-before-make switching to prevent

cross-conduction. An active dead-time reduction circuit

reduces the break-before-make time of the switch to limit the

losses due to current flowing through the synchronous rectifier

body diode.

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