ST10F273 datasheet(10/179 Pages) STMICROELECTRONICS

10 / 179 page

List of figures

ST10F273

10/179

Figure 49.

External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE. . 159

Figure 50.

External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS. . . 160

Figure 51.

External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS . 161

Figure 52.

External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE . . . . . . . 164

Figure 53.

Exteral memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE . . . . . . 165

Figure 54.

External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS . . . . 166

Figure 55.

External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS . . 167

Figure 56.

CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 57.

External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 58.

External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 59.

SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 60.

SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 61.

144-pin plastic quad flat package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 62.

144-pin low profile quad flat package (10x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

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