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ST10F273 数据表(PDF) 47 Page - STMicroelectronics |
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ST10F273 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 179 page  ST10F273 Central processing unit (CPU) 47/179 7.1 Multiplier-accumulator unit (MAC) The MAC coprocessor is a specialized coprocessor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. The standard ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new coprocessor with up to 2 operands per instruction cycle. This new coprocessor (so-called MAC) contains a fast multiply-accumulate unit and a repeat unit. The coprocessor instructions extend the ST10 CPU instruction set with multiply, multiply- accumulate, 32-bit signed arithmetic operations. Figure 6. MAC unit architecture Operand 2 Operand 1 Control Unit Repeat unit ST10 CPU Interrupt controller MSW MRW MAH MAL MCW Flags MAE Mux 8-bit left/right shifter Mux Mux Sign Extend 16 x 16 Concatenation signed/unsigned multiplier 40-bit signed arithmetic unit 0h 0h 08000h 40 16 40 40 32 32 16 40 40 40 40 40 Scaler AB 40 GPR Pointers * IDX0 pointer IDX1 pointer QR0 GPR offset register QR1 GPR offset register QX0 IDX offset register QX1 IDX offset register |
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