ST10F273 datasheet(25/179 Pages) STMICROELECTRONICS

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ST10F273

Internal Flash memory

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Internal Flash memory

5.1

Overview

The on-chip Flash is composed by one matrix module divided in two banks that can be read

and modified indipendently one of the other: one bank can be read while another bank is

under modification. Bank 0 is 384 Kbytes wide, Bank 1 is 128 Kbytes wide.

This module is on ST10 Internal bus, so it is called IFlash.

Figure 4.

Flash structure

The programming operations of the flash are managed by an embedded Flash

Program/Erase Controller (FPEC). The High Voltages needed for Program/Erase operations

are internally generated.

The Data bus is 32-bit wide for fetch accesses to IFlash, while it is 16-bit wide for read

accesses to IFlash. Read/write accesses to IFlash Control Registers area are 16-bit wide.

5.2

Functional description

5.2.1

Structure

Following table shows the Address space reserved to the Flash module.

Bank 1: 128 Kbyte

Bank 0: 384 Kbyte

program memory

HV and Ref.

generator

Program/erase

controller

I-BUS interface

8 Kbyte test-Flash

X-BUS interface

IFlash (Module I)

Control Section

program memory

Flash control

registers

Table 3.

Address space of the Flash module

Description

Addresses

Size

IFlash sectors

0x00 0000 to 0x08 FFFF

512 Kbytes

Registers and Flash internal reserved area

0x0E 0000 to 0x0E FFFF

64 Kbytes

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