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ST10F273 数据表(PDF) 155 Page - STMicroelectronics |
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ST10F273 数据表(HTML) 155 Page - STMicroelectronics |
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155 / 179 page  ST10F273 Electrical characteristics 155/179 24.8.14 Memory cycle variables The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. 24.8.15 External memory bus timing In next sections the external memory bus timings are reported. The given values are computed for a maximum CPU clock of 40 MHz. It is evident that when higher CPU clock frequency is used (up to 64 MHz), some numbers in the timing formulas become zero or negative, that in most of the cases is not acceptable or not meaningful at all. In these cases, it is necessary to relax the speed of the bus setting properly tA, tC and tF. Note: All external memory bus timings and SSC timings reported in the following tables are granted by design characterization and not fully tested in production. Description Symbol Values ALE extension tA TCL x [ALECTL] Memory cycle time wait states tC 2TCL x (15 - [MCTC]) Memory tri-state time tF 2TCL x (1 - [MTTC]) |
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